Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesIntegrated Functions (Continued)4.7 PCI CONTROLLERThe GXLV processor includes an integrated PCI controllerwith the following features.4.7.1 X-Bus PCI Slave• 16-byte PCI write buffer• 16-byte PCI read buffer from X-bus• Supports cache line bursting• Write/Inv line support• Pacing of data for read or write operations with X-bus• No active byte enable transfers supported4.7.2 X-Bus PCI Master• 16byteX-bustoPCIwritebuffer• Configuration read/write Support• Int Acknowledge support• Lock conversion• Support fast back-to-back cycles as slave4.7.3 PCI Arbiter• Fixed, rotating, hybrid, or ping-pong arbitration(programmable)• Support four masters, three on PCI• Internal REQ for CPU• Master retry mask counter• Master dead timer• Resource or total system lock support4.7.4 Generating Configuration CyclesConfiguration space is a physical address space unique toPCI. Configuration Mechanism #1 must be used by softwareto generate configuration cycles. Two DWORD I/Olocations are used in this mechanism. The first DWORDlocation (CF8h) references a read/write register that isnamed CONFIG_ADDRESS. The second DWORDaddress (CFCh) references a register namedCONFIG_DATA. The general method for accessing configurationspace is to write a value intoCONFIG_ADDRESS that specifies a PCI bus, a device onthat bus, and a configuration register in that device beingaccessed. A read or write to CONFIG_DATA will thencause the bridge to translate that CONFIG_ADDRESSvalue to the requested configuration cycle on the PCI bus.4.7.5 Generating Special CyclesA special cycle is a broadcast message to the PCI bus.Two hardcoded special cycle messages are defined in thecommand encode: HALT and SHUTDOWN. Software canalso generate special cycles by using special cycle generationfor configuration mechanism #1 as described in thePCI Specification 2.1 and briefly described here. To initiatea special cycle from software, the host must write avalue to CONFIG_ADDRESS encoded as shown in Table4-40.The next value written to CONFIG_DATA is the encodedspecial cycle. Type 0 or Type 1 conversion will be basedon the Bus Bridge number matching the GXLV processor’sbus number of 00h.Table 4-40. Special Cycle Code to CONFIG_ADDRESS31 30 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 01 0000000 BusNo.=Bridge 1 1 1 1 1 1 1 1 0 0 0 0 0 0CONFIGENABLERSVD BUS NUMBER DEVICE NUMBER FUNCTIONNUMBERNote: See Table 4-41 on page 167, bits [1:0] for translation type.REGISTER NUMBERTRANSLATIONTYPEwww.national.com 166 Revision 1.3
Integrated Functions (Continued)4.7.6 PCI Configuration Space Control RegistersThere are two registers in this category:CONFIG_ADDRESS and CONFIG_DATA.The CONFIG_ADDRESS register contains the addressinformation for the next configuration space access toCONFIG_DATA. Only DWORD accesses are permitted toBit Name DescriptionTable 4-41. PCI Configuration Registersthis register all others will be forwarded as normal I/Ocycles to the PCI bus.The CONFIG_DATA register contains the data that is sentor received during a PCI configuration space access.Table 4-41 gives the bit formats for these two registers.I/O Offset 0CF8h-0CFBh CONFIG_ADDRESS Register (R/W) Default Value = 00000000h31 GFC_EN CONFIG ENABLE: Determines when accesses should be translated to configuration cycles on thePCI bus, or treated as a normal I/O operation. This register will be updated only on full DWORD I/Ooperations to the CONFIG_ADDRESS. Any other accesses are treated as normal I/O cycles inorder to allow I/O devices to use BYTE or WORD registers at the same address and remain unaffected.Once bit 31 is set high, subsequent accesses to CONFIG_DATA are then translated to configurationcycles.1 = Generate configuration cycles.0 = Normal I/O cycles.30:24 RSVD Reserved: Set to 0.23:16 BUS Bus: Specifies a PCI bus number in the hierarchy of 1 to 256 buses.15:11 DEVICE Device: Selects a device on a specified bus. A device value of 00h will select the GXLV processor ifthe bus number is also 00h. DEVICE values of 01h to 15h will be mapped to AD[31:11], so only 21 ofthe 32 possible devices are supported. A DEVICE value of 00001b will map to AD[11] while a deviceof 10101b will map to AD[31].10:8 FUNCTION Function: Selects a function in a multi-function device.7:2 REGISTER Register: Chooses a configuration DWORD space register in the selected device.1:0 TT Translation Type Bits: These bits indicate if the configuration access is local or one that requirestranslation through other bridges to another PCI bus. When an access occurs to the CONFIG_DATAaddress and the specified bus number matches the GXLV processor’s bus number (00h), then aType 0 translation takes place.For a Type 0 translation, the CONFIG_ADDRESS register values are translated to AD lines on thePCI bus. Note that bits [10:2] are passed unchanged. The DEVICE value is mapped to one of 21 ADlines. The translation type bits are set to 00 to indicate a transaction on the local PCI bus.When an access occurs to the CONFIG_DATA address and the specified bus number is not 00h(Type 1), the GXLV processor passes this cycle to the PCI bus by copying the contents of theCONFIG_ADDRESS register onto the AD lines during the address phase of the cycle while drivingthe translation type bits AD[1:0] to 01.Geode GXLV Processor SeriesI/O Offset 0CFCh-0CFFh CONFIG_DATA (R/W) Default Value = 00000000h31:0 CONFIG_DATA Configuration Data Register: Contains the data that is sent or received during a PCI configurationspace access. The register accessed is determined by the value in the CONFIG_ADDRESS register.The CONFIG_DATA register supports BYTE, WORD, or DWORD accesses. To access this register,bit 31 of the CONFIG_ADDRESS register must be set to 0 and a full DWORD I/O access mustbe done. Configuration cycles are performed when bit 31 of the CONFIG_ADDRESS register is setto 1Revision 1.3 167 www.national.com
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Geode GXLV Processor Series Low Pow
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