Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesIntegrated Functions (Continued)4.2.5 Internal Bus Interface Unit RegistersThe Internal Bus Interface Unit maps 100h bytes startingat GX_BASE+8000h. However only 16 bytes (four 32-bitregisters) are defined. Refer to Section 4.1.2 “ControlRegisters” on page 99 for instructions on accessing theseregisters.Table 4-8 summarizes the four 32-bit registers containedin the Internal Bus Interface Unit and Table 4-9 gives theregister/bit formats.Table 4-8. Internal Bus Interface Unit Register SummaryGX_BASE+Memory Offset Type Name/Function8000h-8003h R/W BC_DRAM_TOPTop of DRAM — Contains the highest available address of system memory notincluding the memory that is set aside for graphics memory, which corresponds to1 GB of memory. The largest possible value for the register is 3FFFFFFFh.8004h-8007h R/W BC_XMAP_1Memory X-Bus Map Register 1 (A and B Region Control) — Contains the regioncontrol of the A and B regions and the SMI controls required for VGA emulation.PCI access to internal registers and the A20M function are also controlled by thisregister.8008h-800Bh R/W BC_XMAP_2Memory X-Bus Map Register 2 (C and D Region Control) — Contains region controlfields for eight regions in the address range C0h through DCh.800Ch-800Fh R/W BC_XMAP_3Memory X-Bus Map Register 3 (E and F Region Control) — Contains the regioncontrol fields for memory regions in the address range E0h through FCh.DefaultValue3FFFFFFFh00000000h00000000h00000000hBit Name DescriptionTable 4-9. Internal Bus Interface Unit RegistersGX_BASE+8000h-8003h BC_DRAM_TOP Register (R/W) Default Value = 3FFFFFFFh31:28 RSVD Reserved: Set to 0.27:17 TOP OFDRAMTop of DRAM:000h = Minimum top or 0001FFFFh (128 KB).7FFh = Maximum top or 0FFFFFFFh (256 MB).16:0 RSVD Reserved: Set to 1.GX_BASE+8004h-8007h BC_XMAP_1 Register (R/W) Default Value = 00000000h31:29 RSVD Reserved: Set to 0.28 GEB8 Graphics Enable for B8 Region: Allow memory R/W operations for address range B8000h to BFFFFhbe directed to the graphics pipeline: 0 = Disable; 1 = Enable. If enabled, the GEB8 region is always noncacheable.In the region control field (B8) the cache enable bit (bit 2) is ignored.(Used for VGA emulation.)27:24 B8 B8 Region: Region control field for address range B8000h to BFFFFh.Note: Refer to Table 4-10 on page 106 for decode.23 RSVD Reserved: Set to 0.22 PRAE PCI Register Access Enable: Allow PCI Slave to access internal registers on the X-Bus:0 = Disable; 1 = Enable.21 A20M Address Bit 20 Mask: Address bit 20 is always forced to a zero except for SMI accesses:0 = Disable; 1 = Enable.20 GEB0 Graphics Enable for B0 Region: Allow memory R/W operations for address range B8000h to BFFFFhbe directed to the graphics pipeline: 0 = Disable; 1 = Enable. If enabled, the GEB0 region is always noncacheable.In the region control field (B0) the cache enable bit (bit 2) is ignored.(Used for VGA emulation.)19:16 B0 B0 Region: Region control field for address range B0000h to B7FFFh.Note: Refer to Table 4-10 on page 106 for decode.15 SMID SMID: All I/O accesses for address range 3D0h to 3DFh generate an SMI: 0 = Disable; 1 = Enable.(Used for VGA virtualization.)www.national.com 104 Revision 1.3
Integrated Functions (Continued)Bit Name DescriptionTable 4-9. Internal Bus Interface Unit Registers14 SMIC SMIC: All I/O accesses for address range 3C0h to 3CFh generate an SMI: 0 = Disable; 1 = Enable.(Used for VGA virtualization.)13 SMIB SMIB: All I/O accesses for address range 3B0h to 3BFh generate an SMI: 0 = Disable; 1 = Enable(Used for VGA virtualization.)12:8 RSVD Reserved: Set to 0.7 XPD X-Bus Pipeline: The address for the next cycle can be driven on the X-Bus before the completion of thedata phase of the current cycle.0 = Enable1 = Disable6 GNWS X-BusGraphicsPipeNoWaitState:Data driven on the X-Bus from the graphics pipeline:0 = 1 full clock before X_DSX is asserted1 = On the same clock in which X_RDY is asserted5 XNWS X-Bus No Wait State: Data driven on the X-Bus from the internal bus interface unit:0 = 1 full clock before X_DSX is asserted1 = On the same clock in which X_RDY is asserted4 GEA Graphics Enable for A Region: Allow memory R/W operations for address range B8000h to BFFFFhbe directed to the graphics pipeline: 0 = Disable; 1 = Enable. If enabled, the GEA region is always noncacheable.In the region control field (A0) the cache enable bit (bit2) is ignored.(Used for VGA emulation.)3:0 A0 A0 Region: Region control field for address range A0000h to AFFFFh.Note: Refer to Table 4-10 on page 106 for decode.Geode GXLV Processor SeriesGX_BASE+8008h-800Bh BC_XMAP_2 Register (R/W) Default Value = 00000000h31:28 DC DC Region: Region control field for address range DC000h to DFFFFh.27:24 D8 D8 Region: Region control field for address range D8000h to DBFFFh.23:20 D4 D4 Region: Region control field for address range D4000h to D7FFFh.19:16 D0 D0 Region: Region control field for address range D0000h to D3FFFh.15:12 CC CC Region: Region control field for address range CC000h to CFFFFh.11:8 C8 C8 Region: Region control field for address range C8000h to CBFFF.7:4 C4 C4 Region: Region control field for address range C4000h to C7FFFh.3:0 C0 C0 Region: Region control field for address range C0000h to C3FFFh.Note: Refer to Table 4-10 on page 106 for decode.GX_BASE+800Ch-800Fh BC_XMAP_3 Register (R/W) Default Value = 00000000h31:28 FC FC Region: Region control field for address range FC000h to FFFFFh.27:24 F8 F8 Region: Region control field for address range F8000h to FBFFFh.23:20 F4 F4 Region: Region control field for address range F4000h to F7FFFh.19:16 F0 F0 Region: Region control field for address range F0000h to F3FFFh.15:12 EC EC Region: Region control field for address range EC000h to EFFFFh.11:8 E8 E8 Region: Region control field for address range E8000h to EBFFFh.7:4 E4 E4 Region: Region control field for address range E4000h to E7FFFh.3:0 E0 E0 Region: Region control field for address range E0000h to E3FFFh.Note: Refer to Table 4-10 on page 106 for decode.Revision 1.3 105 www.national.com
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Signal Definitions (Continued)PinNo
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Signal Definitions (Continued)PinNo
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Power Management (Continued)CPU Sus
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Electrical Specifications (Continue
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Instruction Set (Continued)7.5 MMX
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Geode GXLV Processor Series Low Pow
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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