Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesIntegrated Functions (Continued)FFFF FFFFhMAXDRAM MapGraphics Memory(Frame Buffer, etc.)Physical Address MapROM Access(256 KB)PCI AccessGraphics Memory(Frame Buffer, etc.)SMMSystemCodePower Management Registers(See Table 5-1 on page 181)Memory Controller Registers(See Table 4-14 on page 112)Display Controller Registers(See Table 4-28 on page 141)Graphics Pipeline Registers(See Table 4-23 on page 129)Internal Bus IF Unit Registers(See Table 4-8 on page 104)PCI AccessAvailable to the systemScratchpad RAM(See Table 4-3 on page 100)FFFFFFFFh (4 GB)MAXFFFC0000hGX_BASE+8800000hGX_BASE+800000hGX_BASE+400000hGX_BASE+9000hGX_BASE+8500hGX_BASE+8400hGX_BASE+8300hGX_BASE+8100hGX_BASE+8000hGX_BASE+1000hGX_BASE*GBADD or Top of DRAM100000h (1 MB)E8000hE0000hC0000hA0000h (640 KB)Extended MemoryShadowed System BIOSShadowed Video BIOSUMBs andExpansion ROMsSMMSystemCodePCI AccessAvailable to the systemExtended MemorySystem BIOSVideo BIOSUMBs and Expansion ROMsVGA/MDAFrame Buffers(Soft VGA and/or PCA/ISA)*Top of DRAM100000h (1 MB)E8000hE0000hC0000hA0000h (640 KB)Conventional MemoryConventional Memory0h0h* See BC_DRAM_TOP in Table 4-8 on page 104 or MC_GBASE_ADD in Table 4-15 on page 116.Figure 4-2. GXLV Processor Memory Spacewww.national.com 98 Revision 1.3
Integrated Functions (Continued)4.1.2 Control RegistersThe control registers for the GXLV processor use 32 KB ofthe memory map, starting at GX_BASE+8000h (see Figure4-2). This area is divided into internal bus interfaceunit, graphics pipeline, display controller, memory controller,and power management sections:• The internal bus interface unit maps 100h locationsstarting at GX_BASE+8000h.• The graphics pipeline maps 200h locations starting atGX_BASE+8100h.• The display controller maps 100h locations starting atGX_BASE+8300h.• The memory controller maps 100h locations starting atGX_BASE+8400h• GX_BASE+8500h-8FFFh is dedicated to powermanagement registers for the serial packet transmissioncontrol, the user-defined power managementaddress space, Suspend Refresh, and SMI status forSuspend/Resume.The register descriptions are contained in the individualsubsections of this chapter. Accesses to undefined registersin the GXLV processor control register space will notcause a hardware error.4.1.3 Graphics MemoryGraphics memory is allocated from system DRAM by thesystem BIOS. The GXLV processor’s graphics memory ismapped into 4 MB starting at GX_BASE+800000h. Thisarea includes the frame buffer memory and storage forinternal display controller state. The size of the framebuffer is a linear map whose size depends on the user’srequirements (i.e., resolution, color depth, video buffer,compression buffer, font caching, etc.). Frame buffer scanlines are not contiguous in many resolutions, so softwarethat renders to the frame buffer must use a skip count toadvance between scan lines. The display controller canuse the graphics memory that lies between scan lines forthe compression buffer. Accessing graphics memorybetween the end of a scan line and the start of anothercan cause display problems. The skip count for all supportedresolutions is shown in Table 4-2.The graphics memory size is programmed by setting thegraphics memory base address in the memory controller(seeTable4-15onpage113).Displaydriverscommunicatewith system BIOS about resolution changes, toensure that the correct amount of graphics memory isallocated. Since no mechanism exists to recover systemDRAM from the operating system without rebooting whena graphics resolution change requires an increasedamount of graphics memory, the system must be rebooted!Geode GXLV Processor SeriesTable 4-2. Display Resolution Skip CountsScreenResolutionPixelDepthSkipCount640x480 8 bits 1024640x480 16 bits 2048800x600 8 bits 1024800x600 16 bits 20481024x768 8 bits 10241024x768 16 bits 20481280x1024 8 bits 2048Revision 1.3 99 www.national.com
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Geode GXLV Processor SeriesTable of
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Architecture Overview (Continued)Ge
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2.0 Signal DefinitionsThis section
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Signal Definitions (Continued)PinNo
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Signal Definitions (Continued)Table
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Signal Definitions (Continued)PinNo
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Geode GXLV Processor Series Low Pow
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