Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesInstruction Set (Continued)Table 7-9. General Registers Selected by modr/m Fields and w Field16-BitOperation32-BitOperationmod r/m w = 0 w = 1 w = 0 w = 111 000 AL AX AL EAX11 001 CL CX CL ECX11 010 DL DX DL EDX11 011 BL BX BL EBX11 100 AH SP AH ESP11 101 CH BP CH EBP11 110 DH SI DH ESI11 111 BH DI BH EDI7.1.4 reg FieldThe reg field (Table 7-10) determines which general registersare to be used. The selected register is dependent onwhether a 16- or 32-bit operation is current and on thestatus of the w bit.Table 7-10. General Registers Selected by regField16-Bit Operation32-Bit Operationreg w=0 w=1 w=0 w=1000 AL AX AL EAX001 CL CX CL ECX010 DL DX DL EDX011 BL BX BL EBX100 AH SP AH ESP101 CH BP CH EBP110 DH SI DH ESI111 BH DI BH EDI7.1.4.2 sreg3 Field (FS and GS Segment RegisterSelection)The sreg3 field (Table 7-12) is 3-bit field that is similar tothe sreg2 field, but allows use of the FS and GS segmentregisters.Table 7-12. sreg3 Field Encodingsreg3 FieldSegment Register Selected000 ES001 CS010 SS011 DS100 FS101 GS110 Undefined111 Undefined7.1.5 s-i-b Byte (Scale, Indexing, Base)The s-i-b fields provide scale factor, indexing and a basefield for address selection. The ss, index and base fieldsare described next.7.1.5.1 ss Field (Scale Selection)The ss field (Table 7-13) specifies the scale factor used inthe offset mechanism for address calculation. The scalefactormultipliestheindexvaluetoprovideoneofthecomponentsused to calculate the offset address.Table 7-13. ss Field Encodingss FieldScale Factor00 x101 x201 x411 x87.1.4.1 sreg2 Field (ES, CS, SS, DS RegisterSelection)The sreg2 field (Table 7-11) is a 2-bit field that allows oneof the four 286-type segment registers to be specified.Table 7-11. sreg2 Field Encodingsreg2 FieldSegment Register Selected00 ES01 CS10 SS11 DSwww.national.com 210 Revision 1.3
Instruction Set (Continued)7.1.5.2 index Field (Index Selection)The index field (Table 7-14) specifies the index registerused by the offset mechanism for offset address calculation.When no index register is used (index field = 100),the ss value must be 00 or the effective address is undefined.Table 7-14. index Field EncodingIndex FieldIndex Register000 EAX001 ECX010 EDX011 EBX100 none101 EBP110 ESI111 EDI7.1.5.3 Base Field (s-i-b Present)In Table 7-8, the note “s-i-b is present” for certain entriesforces the use of the mod and base field as listed in Table7-15. The first two digits in the first column of Table 7-15identifies the mod bits in the mod r/m byte. The last threedigits in the first column of this table identify the basefields in the s-i-b byte.Table 7-15. mod base Field Encodingmod Fieldwithinmode/rmByte(bits 7:6)base Fieldwithins-i-bByte(bits 2:0)32-Bit Address Modewith mod r/m and s-i-bBytes Present00 000 DS:[EAX+(scaled index)]00 001 DS:[ECX+(scaled index)]00 010 DS:[EDX+(scaled index)]00 011 DS:[EBX+(scaled index)]00 100 SS:[ESP+(scaled index)]00 101 DS:[d32+(scaled index)]00 110 DS:[ESI+(scaled index)]00 111 DS:[EDI+(scaled index)]01 000 DS:[EAX+(scaled index)+d8]01 001 DS:[ECX+(scaled index)+d8]01 010 DS:[EDX+(scaled index)+d8]01 011 DS:[EBX+(scaled index)+d8]01 100 SS:[ESP+(scaled index)+d8]01 101 SS:[EBP+(scaled index)+d8]01 110 DS:[ESI+(scaled index)+d8]01 111 DS:[EDI+(scaled index)+d8]10 000 DS:[EAX+(scaled index)+d32]10 001 DS:[ECX+(scaled index)+d32]10 010 DS:[EDX+(scaled index)+d32]10 011 DS:[EBX+(scaled index)+d32]10 100 SS:[ESP+(scaled index)+d32]10 101 SS:[EBP+(scaled index)+d32]10 110 DS:[ESI+(scaled index)+d32]10 111 DS:[EDI+(scaled index)+d32]Geode GXLV Processor SeriesRevision 1.3 211 www.national.com
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2.0 Signal DefinitionsThis section
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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