Geode GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)4.2 INTERNAL BUS INTERFACE UNITThe GXLV processor’s internal bus interface unit providescontrol and interface functions to the C-Bus and X-Bus.The functions on C-Bus include: processor core, FPU,graphics pipeline, and L1 cache. The functions on X-Businclude: PCI controller, display controller, memory controller,and graphics accelerator. It provides attribute controlfor several sections of memory, and plays an importantpart in the Virtual VGA function.The internal bus interface unit performs functions whichpreviously required the external pins IGNNE# and A20M#.The internal bus interface unit provides configuration controlfor up to 20 different regions within system memory.This includes a top-of-memory register and 19 configurablememory regions in the address space between 640KB and 1 MB. Each region has separate control for readaccess, write access, cacheability, and external PCI masteraccess.In support of VGA emulation, three of the memory regionsare configurable for use by the graphics pipeline and threeI/O ranges can be programmed to generate SMIs.4.2.1 FPU Error SupportThe FERR# (floating point error) and IGNNE# (ignorenumeric error) pins of the 486 microprocessor have beenreplaced with an IRQ13 (interrupt request 13) pin. In DOSsystems, FPU errors are reported by the external vector13. Emulation of this mode of operation is specified byclearing the NE bit (bit 5) in the CR0 register. If the NE bitis active, the IRQ13 output of the GXLV processor isalways driven inactive. If the NE bit is cleared, the GXLVprocessor drives IRQ13 active when the ES bit (bit 7) inthe FPU Status Register is set high. Software mustrespond to this interrupt with an OUT instruction containingan 8-bit operand to F0h or F1h. When the OUT cycleoccurs, the IRQ13 pin is driven inactive and the FPUstarts ignoring numeric errors. When the ES bit is cleared,the FPU resumes monitoring numeric errors.4.2.2 A20M SupportThe GXLV processor provides an A20M bit in theBC_XMAP_1 Register (GX_BASE+ 8004h[21]) to replacethe A20M# pin on the 486 microprocessor. When theA20M bit is set high, all non-SMI accesses will haveaddress bit 20 forced to zero. External hardware must doan SMI trap on I/O locations that toggle the A20M# pin.The SMI software can then change the A20M bit asdesired.This will maintain compatibility with software that dependson wrapping the address at bit 20.4.2.3 SMI GenerationThe Internal Bus Interface Unit can generate SMI interruptswhenever an I/O cycle is in the VGA address rangesof 3B0h to 3BFh, 3C0h to 3CFh and/or 3D0h to 3DFh. Ifan external VGA card is present, the Internal Bus Interfacereset values will not generate an interrupt on VGAaccesses. (Refer to Section 4.6.3 “VGA ConfigurationRegisters” on page 162 for instructions on how to configurethe registers to enable the SMI interrupt.)4.2.4 640 KB to 1 MB RegionThere are 19 configurable memory regions locatedbetween 640 KB and 1 MB. Three of the regions, A0000hto AFFFFh, B0000h to B7FFFh, and B8000h to BFFFFh,are typically used by the graphics subsystem in VGA emulationmode. Each of the these regions has a VGA controlbit that can cause the graphics pipeline to handleaccesses to that section of memory (see Table 4-37 onpage 163). The area between C0000h and FFFFFh isdivided into 16 KB segments to form the remaining 16regions. All 19 regions have four control bits to allow anycombination of read-access, write-access, cache, andexternal PCI Bus Master access capabilities (see Table 4-10 on page 106).Geode GXLV Processor SeriesRevision 1.3 103 www.national.com