Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesProcessor Programming (Continued)Along with the base address of the page table or the pageframe, each DTE or PTE contains attribute bits and apresent bit as illustrated in Table 3-28.If the present bit (P) is set in the DTE, the page table ispresent and the appropriate page table entry is read. If P= 1 in the corresponding PTE (indicating that the page isin memory), the accessed and dirty bits are updated, ifnecessary, and the operand is fetched. Both accessedbits are set (DTE and PTE), if necessary, to indicate thatthe table and the page have been used to translate a linearaddress. The dirty bit (D) is set before the first write is madeto a page.The present bits must be set to validate the remaining bitsin the DTE and PTE. If either of the present bits are notset, a page fault is generated when the DTE or PTE isaccessed. If P = 0, the remaining DTE/PTE bits are availablefor use by the operating system. For example, theoperating system can use these bits to record where onthe hard disk the pages are located. A page fault is alsogenerated if the memory reference violates the page protectionattributes.Translation Look-Aside BufferThe translation look-aside buffer (TLB) is a cache for thepaging mechanism and replaces the two-level page tablelookup procedure for TLB hits. The TLB is a four-way setassociative 32-entry page table cache that automaticallykeeps the most commonly used page table entries in theprocessor. The 32-entry TLB, coupled with a 4 KB pagesize, results in coverage of 128 KB of memory addresses.The TLB must be flushed when entries in the page tablesare changed. The TLB is flushed whenever the CR3 registeris loaded. An individual entry in the TLB can be flushedusing the INVLPG instruction.DTE CacheThe DTE cache caches the two most recent DTEs so thatfuture TLB misses only require a single page table read tocalculate the physical address. The DTE cache is disabledfollowing RESET and can be enabled by setting theDTE_EN bit in CCR4[4] (see CCR4 register on page 53).Table 3-28. Directory Table Entry (DTE) and Page Table Entry (PTE)Bit Name Description31:12 BASE Base Address: Specifies the base address of the page or page table.ADDRESS11:9 AVAILABLE Available: Undefined and available to the programmer.8:7 RSVD Reserved: Unavailable to programmer.6 D Dirty Bit:PTE format — If = 1: Indicates that a write access has occurred to the page.DTE format — Reserved.5 A Accessed Flag: If set, indicates that a read access or write access has occurred to the page.4:3 RSVD Reserved: Set to 0.2 U/S User/Supervisor Attribute:If = 1: Page is accessible by User at privilege level 3.If = 0: Page is accessible by Supervisor only when CPL ≤ 2.1 W/R Write/Read Attribute:If = 1: Page is writable.If = 0: Page is read only.0 P Present Flag:If = 1: The page is present in RAM and the remaining DTE/PTE bits are validatedIf = 0: The page is not present in RAM and the remaining DTE/PTE bits are available for use by the programmer.www.national.com 78 Revision 1.3
Processor Programming (Continued)3.6 INTERRUPTS AND EXCEPTIONSThe processing of either an interrupt or an exceptionchanges the normal sequential flow of a program by transferringprogram control to a selected service routine.Except for SMM interrupts, the location of the selectedservice routine is determined by one of the interrupt vectorsstored in the interrupt descriptor table.True interrupts are hardware interrupts and are generatedby signal sources external to the CPU. All exceptions(including so-called software interrupts) are produced internallyby the CPU.3.6.1 InterruptsExternal events can interrupt normal program executionby using one of the three interrupt pins on the GXLV processor:• Non-maskable Interrupt (No pin, see note)• Maskable Interrupt (INTR pin)• SMM Interrupt (SMI# pin)Note: There is not an NMI pin on the GXLV processor.Generation of an NMI interrupt is not possible. However,software can generate an NMI by setting bit 2 of CCR7.(See the CCR7 register on page 53.)For most interrupts, program transfer to the interrupt routineoccurs after the current instruction has been completed.When the execution returns to the originalprogram, it begins immediately following the interruptedinstruction.The NMI interrupt cannot be masked by software andalways uses interrupt vector two to locate its service routine.Since the interrupt vector is fixed and is suppliedinternally, no interrupt acknowledge bus cycles are performed.This interrupt is normally reserved for unusual situationssuch as parity errors and has priority over INTRinterrupts.Once NMI processing has started, no additional NMIs areprocessed until an IRET instruction is executed, typicallyat the end of the NMI service routine. If the NMI is reassertedbefore execution of the IRET instruction, oneand only one NMI rising edge is stored and then processedafter execution of the next IRET.During the NMI service routine, maskable interrupts maybe enabled. If an unmasked INTR occurs during the NMIservice routine, the INTR is serviced and executionreturns to the NMI service routine following the next IRET.If a HALT instruction is executed within the NMI serviceroutine, the CPU restarts execution only in response toRESET, an unmasked INTR or a System ManagementMode (SMM) interrupt. NMI does not restart CPU executionunder this condition.The INTR interrupt is unmasked when the InterruptEnable Flag (IF, bit 9) in the EFLAGS register is set to 1(See the EFLAGS Register in Table 3-4 on page 46).Except for string operations, INTR interrupts are acknowledgedbetween instructions. Long string operations haveinterrupt windows between memory moves that allowINTR interrupts to be acknowledged.When an INTR interrupt occurs, the CPU performs aninterrupt-acknowledge bus cycle. During this cycle, theCPU reads an 8-bit vector that is supplied by an externalinterrupt controller. This vector selects which of the 256possible interrupt handlers will be executed in response tothe interrupt.The SMM interrupt has higher priority than either INTR orNMI. After SMI# is asserted, program execution is passedto an SMM service routine that runs in SMM addressspace reserved for this purpose. The remainder of thissection does not apply to the SMM interrupts. SMM interruptsare described in greater detail later in Section 3.7“System Management Mode” on page 83.3.6.2 ExceptionsExceptions are generated by an interrupt instruction or aprogram error. Exceptions are classified as traps, faults oraborts depending on the mechanism used to report themand the restartability of the instruction which first causedthe exception.A Trap exception is reported immediately following theinstruction that generated the trap exception. Trap exceptionsare generated by execution of a software interruptinstruction (INTO, INT3, INTn, BOUND), by a single-stepoperation or by a data breakpoint.Software interrupts can be used to simulate hardwareinterrupts. For example, an INTn instruction causes theprocessor to execute the interrupt service routine pointedto by the nth vector in the interrupt table. Execution of theinterrupt service routine occurs regardless of the state ofthe IF flag (bit 9) in the EFLAGS register.The one byte INT3, or breakpoint interrupt (vector 3), is aparticular case of the INTn instruction. By inserting thisone byte instruction in a program, the user can set breakpointsin the code that can be used during debug.Geode GXLV Processor SeriesRevision 1.3 79 www.national.com
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Geode GXLV Processor Series Low Pow
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