Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesProcessor Programming (Continued)Table 3-27. 16-Bit Task State Segment (TSS) Table15 0Selector for Task’s LDT+2AhDS +28hSS +26hCS +24hES +22hDI +20hSI+1EhBP+1ChSP+1AhBX +18hDX +16hCX +14hAX +12hFLAGS +10hIP+EhSS for Privilege Level 0+ChSP for Privilege Level 1+AhSS for Privilege Level 1 +8hSP for Privilege Level 1 +6hSS for Privilege Level 0 +4hSP for Privilege Level 0 +2hBack Link (Old TSS Selector) +0hwww.national.com 76 Revision 1.3
Processor Programming (Continued)3.5.4 Paging MechanismThe paging mechanism translates a linear address to itscorresponding physical address. If the required page isnot currently present in RAM, an exception is generated.When the operating system services the exception, therequired page can be loaded into memory and the instructionrestarted. Pages are either 4 KB or 1 MB in size. TheCPU defaults to 4 KB pages that are aligned to 4 KBboundaries.A page is addressed by using two levels of tables as illustratedin Figure 3-8. Bits [31:22] of the 32-bit linearaddress, the Directory Table Index (DTI), are used tolocate an entry in the page directory table. The pagedirectory table acts as a 32-bit master index to up to 1 KBindividual second-level page tables. The selected entry inthe page directory table, referred to as the directory tableentry (DTE), identifies the starting address of the secondlevelpage table. The page directory table itself is a pageandisthereforealignedtoa4KBboundary.Thephysicaladdress of the current page directory table is stored in theCR3 control register, also referred to as the Page DirectoryBase Register (PDBR).Bits [21:12] of the 32-bit linear address, referred to as thePage Table Index (PTI), locate a 32-bit entry in the second-levelpage table. This page table entry (PTE) containsthe base address of the desired page frame. The secondlevelpage table addresses up to 1K individual pageframes. A second-level page table is 4 KB in size and isitself a page. Bits [11:0] of the 32-bit linear address, thePage Frame Offset (PFO), locate the desired physicaldata within the page frame.Since the page directory table can point to 1 KB pagetables, and each page table can point to 1 KB pageframes, a total of 1 MB page frames can be implemented.Each page frame contains 4 KB, therefore, up to 4 GB ofvirtual memory can be addressed by the CPU with a singlepagedirectorytable.Geode GXLV Processor SeriesLinearAddress31 22 21 12 11 0Directory Table Index(DTI)Page Table Index(PTI)Page Frame Offset(PFO)4GBDTE Cache2-EntryFully Associative10Main TLB32-Entry4-Way SetAssociative310-4 KB4KB4KBPhysical PageDTEPTE-0CR3ControlRegister00Directory Table Page Table MemoryExternal Memory0Figure 3-8. Paging MechanismRevision 1.3 77 www.national.com
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Architecture Overview (Continued)Ge
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2.0 Signal DefinitionsThis section
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Electrical Specifications (Continue
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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