Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesIntegrated Functions (Continued)4.5 DISPLAY CONTROLLERThe GXLV processor incorporates a display controller thatretrieves display data from the memory controller and formatsit for output on a variety of display devices. TheGXLV processor connects directly to the graphics GeodeI/O companion. The display controller includes a displayFIFO, compression/decompression (codec) hardware,hardware cursor, a 256-entry-by-18-bit palette RAM (plusMemoryData32CompressedLine Buffer(64x32 bit)DisplayFIFO(64x64 bit)6432CodecCursorLatch82PaletteAddr.Logic916three extension colors), display timing generator, ditherand frame-rate-modulation circuitry for TFT panels, andversatile output formatting logic. A diagram of the displaycontroller subsystem is shown in Figure 4-14.ExtensionsPaletteRAM(264x18bit)1818DitherandFRMPseudo/TrueColor MuxOutputFormat818VideoGraphics9MemoryAddress20MemoryAddressGeneratorControl RegistersandControl LogicTimingGeneratorOutputControlFigure 4-14. Display Controller Block Diagramwww.national.com 134 Revision 1.3
Integrated Functions (Continued)4.5.1 Display FIFOThe display controller contains a large (64x64 bit) FIFO forqueuing up display data from the memory controller asrequired for output to the screen. The memory controllermust arbitrate between display controller requests andother requests for memory access from the microprocessorcore, L1 cache controller, and the graphics pipeline.Displaydataisrequiredinrealtime,makingitthehighestpriority in the system. Without efficient memory management,system performance would suffer dramatically dueto the constant display-refresh requests from the displaycontroller. The large size of the display FIFO is desirableso that the FIFO may primarily be loaded during timeswhen there is no other request pending to the DRAM controllerwhich allows the memory controller to stay in pagemode for a longer period of time when servicing the displayFIFO. When a priority request from the cache orgraphics pipeline occurs, if the display FIFO has enoughdata queued up, the DRAM controller can immediatelyservice the request without concern that the display FIFOwill underflow. If the display FIFO is below a programmablethreshold, a high-priority request will be sent to theDRAM controller, which will take precedence over anyother requests that are pending.The display FIFO is 64 bits wide to accommodate highspeedburst read operations from the DRAM controller atmaximum memory bandwidth. In addition to the normalpixel data stream, the display FIFO also queues up cursorpatterns.4.5.2 Compression TechnologyTo reduce the system memory contention caused by thedisplay refresh, the display controller contains compressionand decompression logic for compressing the framebuffer image in real time as it is sent to the display. It combinesthis compressed display buffer into the extra offscreenmemory within the graphics memory aperture.Coherency of the compressed display buffer is maintainedby use of dirty and valid bits for each line. The dirty andvalid RAM is contained on-chip for maximum efficiency.Whenever a line has been validly compressed, it will beretrieved from the compressed display buffer for all futureaccesses until the line becomes dirty again. Dirty lines willbe retrieved from the normal uncompressed frame buffer.The compression logic has the ability to insert a programmablenumber of "static" frames, during which time dirtybits are ignored and the valid bits are read to determinewhether a line should be retrieved from the frame buffer orcompressed display buffer. The less frequently the dirtybits are sampled, the more frequently lines will beretrieved from the compressed display buffer. This allowsa programmable screen image update rate (as opposed torefresh rate). Generally, an update rate of 30 frames persecond is adequate for displaying most types of data,including real-time video. If a flat panel display is used thathas a slow response time, such as 100 ms, the imageneed not be updated faster than ten frames per second,since the panel could not display changes beyond thatrate.The compression algorithm used in the GXLV processorcommonly achieves compression ratios between 10:1 and20:1, depending on the nature of the display data. Thishigh level of compression provides higher system performanceby reducing typical latency for normal systemmemory access, higher graphics performance by increasingavailable drawing bandwidth to the DRAM array, andmuch lower power consumption by significantly reducingthe number of off-chip DRAM accesses required forrefreshing the display. These advantages become evenmore pronounced as display resolution, color depth, andrefresh rate are increased and as the size of the installedDRAM increases.As uncompressed lines are fed to the display, they will becompressed and stored in an on-chip compressed linebuffer (64x32 bits). Lines will not be written back to thecompressed display buffer in the DRAM unless a validcompression has resulted, so there is no penalty forpathological frame buffer images where the compressionalgorithm breaks down.Geode GXLV Processor SeriesRevision 1.3 135 www.national.com
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Geode GXLV Processor Series Low Pow
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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