Geode GXLV Processor Series Low Power Integrated x86 Solutions

Geode GXLV Processor SeriesProcessor Programming (Continued)3.3.3 Model Specific Register SetThe Model Specific Register (MSR) Set is used to monitorthe performance of the processor or a specific componentwithin the processor.A MSR can be read using the RDMSR instruction, opcode0F32h. During a MSR read, the contents of the particularMSR, specified by the ECX register, is loaded into theEDX:EAX registers.A MSR can be written using the WRMSR instruction,opcode 0F30h. During a MSR write, the contents ofEDX:EAX are loaded into the MSR specified in the ECXregister.The RDMSR and WRMSR instructions are privilegedinstructions.The GXLV processor contains one 64-bit model specificregister (MSR10) the Time Stamp Counter (TSC).3.3.4 Time Stamp CounterThe TSC, (MSR[10]), is a 64-bit counter that counts theinternal CPU clock cycles since the last reset. The TSCuses a continuous CPU core clock and will continue tocount clock cycles unless the processor is in Suspend.The TSC is read using a RDMSR instruction, opcode0F32h, with the ECX register set to 10h. During a TSCread, the contents of the TSC is loaded into the EDX:EAXregisters.The TSC is written to using a WRMSR instruction, opcode0F30h with the ECX register set to 10h. During a TSCwrite, the contents of EDX:EAX are loaded into the TSC.The RDMSR and WRMSR instructions are privilegedinstructions.In addition, the TSC can be read using the RDTSCinstruction, opcode 0F31h. The RDTSC instruction loadsthe contents of the TSC into EDX:EAX. The use of theRDTSC instruction is restricted by the TSC flag (bit 2) inthe CR4 register (refer to Tables 3-6 and 3-7 on page 48for CR4 register information). When the TSC bit = 0, theRDTSC instruction can be executed at any privilege level.When the TSC bit = 1, the RDTSC instruction can only beexecuted at privilege level 0.www.national.com 62 Revision 1.3