Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesInstruction Set (Continued)7.4 FPU INSTRUCTION SETThe processor core is functionally divided into the FPU,and the integer unit. The FPU processes floating pointinstructions only and does so in parallel with the integerunit.For example, when the integer unit detects a floating pointinstruction without memory operands, after two clockcycles the instruction passes to the FPU for execution.The integer unit continues to execute instructions whilethe FPU executes the floating point instruction. If anotherFPU instruction is encountered, the second FPU instructionis placed in the FPU queue. Up to four FPU instructionscan be queued. In the event of an FPU exception,while other FPU instructions are queued, the state of theCPU is saved to ensure recovery.The FPU instruction set is summarized in Table 7-29. Thetable uses abbreviations that are described Table 7-28.Table 7-28. FPU Instruction Set Table LegendAbbr.nTOSST(1)ST(n)M.WIM.SIM.LIM.SRM.DRM.XRM.BCDCCEnv RegsDescriptionStack register number.Top of stack register pointed to by SSS in thestatus register.FPU register next to TOS.A specific FPU register, relative to TOS.16-bit integer operand from memory.32-bit integer operand from memory.64-bit integer operand from memory.32-bit real operand from memory.64-bit real operand from memory.80-bit real operand from memory.18-digit BCD integer operand from memory.FPU condition code.Status, Mode Control and Tag Registers,Instruction Pointer and Operand Pointer.www.national.com 228 Revision 1.3
Instruction Set (Continued)Table 7-29. FPU Instruction Set SummaryFPU InstructionClockOpcode OperationCountIssueF2XM1 Function Evaluation 2 x -1 D9 F0 TOS
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2.0 Signal DefinitionsThis section
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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