Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesProcessor Programming (Continued)3.9.3 Privilege Level TransfersA task’s CPL can be changed only through intersegmentcontrol transfers using gates or task switches to a codesegment with a different privilege level. Control transfersresult from exception and interrupt servicing and fromexecution of the CALL, JMP, INT, IRET and RET instructions.There are five types of control transfers that are summarizedin Table 3-37. Control transfers can be made onlywhen the operation causing the control transfer referencesthe correct descriptor type. Any violation of these descriptorusage rules causes a general protection fault.Any control transfer that changes the CPL within a taskresults in a change of stack. The initial values for the stacksegment (SS) and stack pointer (ESP) for privilege levels0, 1, and 2 are stored in the TSS. During a JMP or CALLcontrol transfer, the SS and ESP are loaded with the newstack pointer and the previous stack pointer is saved onthe new stack. When returning to the original privilegelevel, the RET or IRET instruction restores the SS andESP of the less-privileged stack.Table 3-37. Descriptor Types Used for Control TransferType of Control TransferOperation TypesDescriptorReferencedDescriptorTableIntersegment within the same privilegelevel.Intersegment to the same or a moreprivileged level. Interrupt within task(could change CPL level).JMP, CALL, RET, IRET* Code Segment GDT or LDTCALL Gate Call GDT or LDTInterrupt Instruction, Exception, Trap or Interrupt Gate IDTExternal InterruptIntersegment to a less privileged level RET, IRET* Code Segment GDT or LDT(changes task CPL).Task Switch via TSS CALL, JMP Task State Segment GDTTask Switch via Task Gate CALL, JMP Task Gate GDT or LDTIRET**, Interrupt Instruction,Exception, External InterruptTask GateIDTNote: *NT = 0 (Nested Task bit in EFLAGS, bit 14)**NT =1 (Nested Task bit in EFLAGS, bit 14)www.national.com 92 Revision 1.3
Processor Programming (Continued)3.9.3.1 GatesGate descriptors described in Section “Gate Descriptors”on page 74, provide protection for privilege transfersamong executable segments. Gates are used to transitionto routines of the same or a more privileged level. Callgates, interrupt gates and trap gates are used for privilegetransfers within a task. Task gates are used to transferbetween tasks.Gates conform to the standard rules of privilege. In otherwords, gates can be accessed by a task if the effectiveprivilege level (EPL) is the same or more privileged thanthe gate descriptor’s privilege level (DPL).3.9.4 Initialization and Transition to Protected ModeThe GXLV processor core switches to real mode immediatelyafter RESET. While operating in real mode, the systemtables and registers should be initialized. The GDTRand IDTR must point to a valid GDT and IDT, respectively. Thesize of the IDT should be at least 256 bytes, and the GDTmust contain descriptors that describe the initial code anddata segments.Theprocessorcanbeplacedinprotectedmodebysettingthe PE bit (CR0 register bit 0). After enabling protectedmode, the CS register should be loaded and the instructiondecode queue should be flushed by executing anintersegment JMP. Finally, all data segment registersshould be initialized with appropriate selector values.3.10 VIRTUAL 8086 MODEBoth real mode and virtual 8086 (V86) modes are supportedby the GXLV processor, allowing execution of 8086application programs and 8086 operating systems. V86mode allows the execution of 8086-type applications, yetstill permits use of the paging and protection mechanisms.V86 tasks run at privilege level 3. Before entry, all segmentlimits must be set to FFFFh (64K) as in real mode.3.10.1 Memory AddressingWhile in V86 mode, segment registers are used in anidentical fashion to real mode. The contents of the Segmentregister are multiplied by 16 and added to the offsetto form the Segment Base Linear Address. The GXLV processorpermits the operating system to select which programsuse the V86 address mechanism and whichprograms use protected mode addressing for each task.The GXLV processor also permits the use of paging whenoperating in V86 mode. Using paging, the 1 MB addressspace of the V86 task can be mapped to any region in the4 GB linear address space.The paging hardware allows multiple V86 tasks to runconcurrently, and provides protection and operating systemisolation. The paging hardware must be enabled torun multiple V86 tasks or to relocate the address space ofa V86 task to physical address space other than 0.3.10.2 ProtectionAll V86 tasks operate with the least amount of privilege(level 3) and are subject to all CPU protected mode protectionchecks. As a result, any attempt to execute a privilegedinstruction within a V86 task results in a generalprotection fault.In V86 mode, a slightly different set of instructions aresensitive to the I/O privilege level (IOPL) than in protectedmode. These instructions are: CLI, INT n, IRET, POPF,PUSHF, and STI. The INT3, INTO and BOUND variationsof the INT instruction are not IOPL sensitive.3.10.3 Interrupt HandlingTo fully support the emulation of an 8086-type machine,interrupts in V86 mode are handled as follows. When aninterrupt or exception is serviced in V86 mode, programexecution transfers to the interrupt service routine at privilegelevel 0 (i.e., transition from V86 to protected modeoccurs). The VM bit in the EFLAGS register (bit 17) iscleared. The protected mode interrupt service routinethen determines if the interrupt came from a protectedmode or V86 application by examining the VM bit in theEFLAGS image stored on the stack. The interrupt serviceroutine may then choose to allow the 8086 operating systemto handle the interrupt or may emulate the function ofthe interrupt handler. Following completion of the interruptservice routine, an IRET instruction restores the EFLAGSregister (restores VM = 1) and segment selectors andcontrol returns to the interrupted V86 task.3.10.4 Entering and Leaving Virtual 8086 ModeV86 mode is entered from protected mode by either executingan IRET instruction at CPL = 0 or by task switching.If an IRET is used, the stack must contain an EFLAGSimage with VM = 1. If a task switch is used, the TSS mustcontain an EFLAGS image containing a 1 in the VM bitposition. The POPF instruction cannot be used to enterV86 mode since the state of the VM bit is not affected.V86 mode can only be exited as the result of an interruptor exception. The transition out must use a 32-bit trap orinterrupt gate that must point to a non-conforming privilegelevel 0 segment (DPL = 0), or a 32-bit TSS. Theserestrictions are required to permit the trap handler to IRETback to the V86 program.Geode GXLV Processor SeriesRevision 1.3 93 www.national.com
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Geode GXLV Processor Series Low Pow
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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