Geode GXLV Processor Series Low Power Integrated x86 Solutions

Geode GXLV Processor SeriesProcessor Programming (Continued)Along with the base address of the page table or the pageframe, each DTE or PTE contains attribute bits and apresent bit as illustrated in Table 3-28.If the present bit (P) is set in the DTE, the page table ispresent and the appropriate page table entry is read. If P= 1 in the corresponding PTE (indicating that the page isin memory), the accessed and dirty bits are updated, ifnecessary, and the operand is fetched. Both accessedbits are set (DTE and PTE), if necessary, to indicate thatthe table and the page have been used to translate a linearaddress. The dirty bit (D) is set before the first write is madeto a page.The present bits must be set to validate the remaining bitsin the DTE and PTE. If either of the present bits are notset, a page fault is generated when the DTE or PTE isaccessed. If P = 0, the remaining DTE/PTE bits are availablefor use by the operating system. For example, theoperating system can use these bits to record where onthe hard disk the pages are located. A page fault is alsogenerated if the memory reference violates the page protectionattributes.Translation Look-Aside BufferThe translation look-aside buffer (TLB) is a cache for thepaging mechanism and replaces the two-level page tablelookup procedure for TLB hits. The TLB is a four-way setassociative 32-entry page table cache that automaticallykeeps the most commonly used page table entries in theprocessor. The 32-entry TLB, coupled with a 4 KB pagesize, results in coverage of 128 KB of memory addresses.The TLB must be flushed when entries in the page tablesare changed. The TLB is flushed whenever the CR3 registeris loaded. An individual entry in the TLB can be flushedusing the INVLPG instruction.DTE CacheThe DTE cache caches the two most recent DTEs so thatfuture TLB misses only require a single page table read tocalculate the physical address. The DTE cache is disabledfollowing RESET and can be enabled by setting theDTE_EN bit in CCR4[4] (see CCR4 register on page 53).Table 3-28. Directory Table Entry (DTE) and Page Table Entry (PTE)Bit Name Description31:12 BASE Base Address: Specifies the base address of the page or page table.ADDRESS11:9 AVAILABLE Available: Undefined and available to the programmer.8:7 RSVD Reserved: Unavailable to programmer.6 D Dirty Bit:PTE format — If = 1: Indicates that a write access has occurred to the page.DTE format — Reserved.5 A Accessed Flag: If set, indicates that a read access or write access has occurred to the page.4:3 RSVD Reserved: Set to 0.2 U/S User/Supervisor Attribute:If = 1: Page is accessible by User at privilege level 3.If = 0: Page is accessible by Supervisor only when CPL ≤ 2.1 W/R Write/Read Attribute:If = 1: Page is writable.If = 0: Page is read only.0 P Present Flag:If = 1: The page is present in RAM and the remaining DTE/PTE bits are validatedIf = 0: The page is not present in RAM and the remaining DTE/PTE bits are available for use by the programmer.www.national.com 78 Revision 1.3