Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesProcessor Programming (Continued)3.11 FLOATING POINT UNIT OPERATIONSThe GXLV processor contains an FPU that is x87 andMMX instruction-set compatible and adheres to the IEEE-754 standard. Because most applications that containFPU instructions intermix with integer instructions, theGXLV processor’s FPU achieves high performance bycompleting integer and FPU operations in parallel.3.11.1 FPU Register SetThe FPU provides the user eight data registers, a controlregister, and a status register. The CPU also provides adata register tag word that improves context switching andstack performance by maintaining empty/non-empty statusfor each of the eight data registers. Two additional,registers contain pointers to (a) the memory location containingthe current instruction word and (b) the memorylocation containing the operand associated with the currentinstruction word (if any).3.11.2 FPU Tag Word RegisterThe FPU maintains a tag word register that is divided intoeight tag word fields. These fields assume one of four valuesdepending on the contents of their associated dataregisters: Valid (00), Zero (01), Special (10), and Empty(11). Note: Denormal, Infinity, QNaN, SNaN and unsupportedformats are tagged as “Special”. Tag values aremaintained transparently by the CPU and are only availableto the programmer indirectly through the FSTENV andFSAVE instructions. The tag word with TAG fields for eachassociated physical register, TAG(n), is shown in Table 3-38.3.11.3 FPU Status RegisterThe FPU communicates status information and operationresults to the CPU through the FPU status register, whosefields are detailed in Table 3-38. These fields include informationrelated to exception status, operation executionstatus, register status, operand class, and comparisonresults. This register is continuously accessible to theCPU regardless of the state of the Control or ExecutionUnits.3.11.4 FPU Mode Control RegisterThe FPU Mode Control Register, shown in Table 3-38, isused by the GXLV processor to specify the operatingmode of the FPU. The register fields include informationrelated to the rounding mode selected, the amount of precisionto be used in the calculations, and the exceptionconditions which should be reported to the GXLV processorusing traps. The user controls precision, rounding,and exception reporting by setting or clearing appropriatebits.www.national.com 94 Revision 1.3
Processor Programming (Continued)Bit Name DescriptionTable 3-38. FPU RegistersFPU Tag Word Register (R/W) (Note)15:14 TAG7 TAG7: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.13:12 TAG6 TAG6: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.11:10 TAG5 TAG5: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.9:8 TAG4 TAG4: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.7:6 TAG3 TAG3: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.5:4 TAG2 TAG2: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.3:2 TAG1 TAG1: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.1:0 TAG0 TAG0: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.FPU Status Register (R/W) (Note)15 B Copy of ES bit (bit 7 this register)14 C3 Condition code bit 313:11 S Top-of-Stack: Register number that points to the current TOS.10:8 C[2:0] Condition code bits [2:0]7 ES Error indicator: Set to 1 if unmasked exception detected.6 SF Stack Full: FPU Status Register: or invalid register operation bit.5 P Precision error exception bit4 U Underflow error exception bit3 O Overflow error exception bit2 Z Divide-by-zero exception bit1 D Denormalized-operand error exception bit0 I Invalid operation exception bitFPU Mode Control Register (R/W) (Note)15:12 RSVD Reserved: Set to 011:10 RC Rounding control bits:00 = Round to nearest or even01 = Round towards minus infinity10 = Round towards plus infinity11 = Truncate9:8 PC Precision control bits:00 = 24-bit mantissa01 = Reserved10 = 53-bit mantissa11 = 64-bit mantissa7:6 RSVD Reserved: Set to 05 P Precision error exception bit4 U Underflow error exception bit3 O Overflow error exception bit2 Z Divide-by-zero exception bit1 D Denormalized-operand error exception bit0 I Invalid-operation exception bitNote: R/W only through the environment at store and restore commands.Geode GXLV Processor SeriesRevision 1.3 95 www.national.com
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Signal Definitions (Continued)PinNo
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Geode GXLV Processor Series Low Pow
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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