Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesIntegrated Functions (Continued)4.5.3 Hardware CursorThe display controller contains hardware cursor logic toallow overlay of the cursor image onto the pixel datastream. Overhead for updating this image on the screen iskept to a minimum by requiring that only the X and Y positionbe changed. This eliminates "submarining" effectscommonly associated with software cursors. The cursor,32x32 pixels with 2-bpp, is loaded into off-screen memorywithin the graphics memory aperture. TheDC_CUR_ST_OFFSET programs the cursor start (seeTable 4-30 on page 148). The 2-bit code selects color 0,color 1, transparent, or background-color inversion foreach pixel in the cursor. The two cursor colors will bestored as extensions to the normal 256-entry palette atlocations 100h and 101h.The 2-bit cursor codes are as follows:AND XOR Displayed0 0 Cursor Color 00 1 Cursor Color 11 0 Transparent − Background Pixel1 1 Inverted − Bit-wise Inversion of BackgroundPixelThe cursor overlay patterns are loaded to independentmemory locations, usually mapped above the frame bufferand compressed display buffer (off-screen). The cursorbuffer must start on a DWORD boundary. It is linearlymapped, and is always 256 bytes in size. If there isenough room (256 bytes) after the compression-buffer linebut before the next frame-buffer line starts, the cursor patternmay be loaded into this area to make efficient use ofthe graphics memory.Each pattern is a 32x32-pixel array of 2-bit codes. Thecodes are a combination of AND mask and XOR mask fora particular pixel. Each line of an overlay pattern is storedas two DWORDs, with each DWORD containing the ANDmasks for 16 pixels in the upper word and the XOR masksfor 16 pixels in the lower word. DWORDs are arrangedwith the leftmost pixel block being least significant and therightmost pixel block being most significant. Pixels withinwords are arranged with the leftmost pixels being mostsignificant and the rightmost pixels being least significant.Multiple cursor patterns may be loaded into the off-screenmemory. An application may simply change the cursorstart offset to select a new cursor pattern. The new cursorpattern will become effective at the start of the next framescan.4.5.4 Display Timing GeneratorThe display controller features a fully programmable timinggenerator for generating all timing control signals forthe display. The timing control signals include horizontaland vertical sync and blank signals in addition to timing foractive and overscan regions of the display. The timinggenerator is similar in function to the CRTC of the originalVGA, although programming is more straightforward. Programmingof the timing registers are supported byNational via a BIOS INT10 call during a mode set. Whenprogramming the timing registers directly, extreme careshould be taken to ensure that all timing is compatible withthe display device.The timing generator supports overscan to maintain fullbackward compatibility with the VGA standard. This featureis supported primarily for CRT display devices sinceflat panel displays have fixed resolutions and do not providefor overscan. When a display mode is selected havinga lower resolution than the panel resolution, the GXLVprocessor supports a mechanism to center the display bystretching the border to fill the remainder of the screen.The border color is at palette extension 104h.4.5.5 Dither and Frame Rate ModulationThe display controller supports 2x2 dither and two-levelframe rate modulation (FRM) to increase the apparentnumber of colors displayed on 9-bit or 12-bit TFT panels.Dither and FRM are individually programmable. With ditheringand FRM enabled, 185,193 colors are possible on a9-bit TFT panel, and 226,981 colors are possible on a 12-bit TFT panel.4.5.6 Display ModesThe GXLV processor’s display controller is programmableand supports resolutions up to 1024x768 at 16 bits perpixel and resolutions up to 1280x1024 at 8 bits per pixel.This means the GXLV processor supports the standarddisplay resolutions of 640x480, 800x600, and 1024x768display resolutions at both 8 and 16 bits per pixel and1280x1024 resolution at 8 bits per pixel only. Two 16-bitdisplay formats are supported: RGB 5-6-5 and RGB 5-5-5. Table 4-26 lists how the RGB data is mapped onto thepixel data bus for the CRT and various TFT interfaces. AllCRT modes can have VESA-compatible timing. Table 4-25 lists some of the supported TFT panel display modesand Table 4-27 lists some of the supported CRT displaymodes.www.national.com 136 Revision 1.3
Integrated Functions (Continued).Resolution640x480(Note 5)800x600(Note 5)1024x768Notes: 1.SimultaneousColors8-bpp256 colors out of apalette of 25616-bpp64 KB colors5-6-58-bpp256 colors out of apalette of 25616-bpp64 KB Colors5-6-58-bpp256 colors out of apalette of 25616-bpp64 KB colors5-6-5Table 4-25. TFT Panel Display Modes (Note 1)RefreshRate(Hz)DCLKRate(MHz)(Note 2)PCLKRate(MHz)(Note 3)PanelTypeMaximum DisplayedColors (Note 4)60 50.35 25.175 9-bit 57 3 = 185,19312-bit 61 3 = 226,98118-bit 4 3 = 262,14460 50.35 25.175 9-bit 29x57x29 = 47,93712-bit 31x61x31 = 58,62118-bit 32x64x32 = 65,53560 80.0 40.0 9-bit 57 3 = 185,19312-bit 61 3 = 226,98118-bit 64 3 = 262,14460 80.0 40.0 9-bit 29x57x29 = 47,93712-bit 31x61x31 = 58,62118-bit 32x64x32 = 65,53560 65 65.0 9-bit/18-I/F 57 3 = 185,19360 65 65.0 9-bit/18-I/F 29x57x29 = 47,937This list is not meant to be an complete list of all the possible supported TFT display modes.2. DCLK is the input clock from the Geode I/O companion. In some cases, DCLK is doubled to keep theGeode I/O companion’s PLL in a desired operational range.3. PCLK is the graphics output clock to the Geode I/O companion.4. 9-bit and 12-bit panels use FRM and dither to increase displayed colors. (See Section 4.5.5 “Dither andFrame Rate Modulation” on page 136.)5. All 640x480 and 800x600 modes can be run in simultaneous display with CRTGeode GXLV Processor SeriesRevision 1.3 137 www.national.com
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Geode GXLV Processor Series Low Pow
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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