Geode GXLV Processor Series Low Power Integrated x86 Solutions

Power Management (Continued)5.2.2 Initiating Suspend with SUSP#The GXLV processor enters the Suspend mode inresponse to SUSP# input assertion only when certainconditions are met. First, the USE_SUSP bit must be setin CCR2 (Index C2h[7]). In addition, execution of the currentinstructions and any pending decoded instructionsand associated bus cycles must be completed. SUSP# issampled on the rising edge of SYSCLK, and must meetspecified setup and hold times to be recognized at a particularSYSCLK edge. See Figure 5-2 for timing details.When all conditions are met, the SUSPA# output isasserted. The time from assertion of SUSP# to the activationof SUSPA# depends on which instructions weredecoded prior to assertion of SUSP#. Normally, onceSUSP# has been sampled inactive the SUSPA# outputwill be deactivated within two clocks. However, the deactivationof SUSPA# may be delayed until the end of anactive refresh cycle.If the CPU is already in a Suspend mode initiated bySUSP#, one occurrence of INTR and SMI# is stored forexecution after Suspend mode is exited. The CPU alsoallows PCI master accesses during a SUSP#-initiatedSuspendmode.SeeFigure5-3fortimingdetails.Ifanunmasked REQx# is asserted, the GXLV processor willdeassert SUSPA# and exit Suspend mode to respond tothe PCI master access. If SUSP# is asserted when thePCI master access is completed, REQx# deasserted, theGXLV processor will reassert SUSPA# and return to aSUSP#-initiated Suspend mode. If the CPU is in the middleof a PCI master access when SUSP# is asserted, theassertion of SUSPA# will be delayed until the PCI accessis completed.Geode GXLV Processor SeriesSYSCLKSUSP#SUSPA#Figure 5-2. SUSP#-Initiated Suspend ModeSYSCLKREQx#FRAME#TRDY#SUSP#SUSPA#Figure 5-3. PCI Access During Suspend ModeRevision 1.3 179 www.national.com