Geode GXLV Processor Series Low Power Integrated x86 Solutions

Geode GXLV Processor SeriesInstruction Set (Continued)7.2 CPUID INSTRUCTIONThe CPUID instruction (opcode 0FA2) allows the softwareto make processor inquiries as to the vendor, family,model, stepping, features and also provides cache information.The GXLV supports both the standard andNational Semiconductor extended CPUID levels.The presence of the CPUID instruction is indicated by theability to change the value of the ID Flag, bit 21 in theEFLAGS register.The CPUID level allows the CPUID instruction to returndifferent information in the EAX, EBX, ECX, and EDX registers.The level is determined by the initialized value ofthe EAX register before the instruction is executed. Asummary of the CPUID levels is shown in Table 7-16.CPUIDTypeTable 7-16. CPUID Levels SummaryInitializedEAXRegisterReturned Data in EAX, EBX,ECX, EDX RegistersStandard 0000 0000h Maximum standard levels, CPUvendor stringStandard 0000 0001h Model, family, type and featuresStandard 0000 0002h TLB and cache informationExtended 8000 0000h Maximum extended levelsExtended 8000 0001h Extended model, family, type andfeaturesExtended 8000 0002h CPU marketing name stringExtended 8000 0003hExtended 8000 0004hExtended 8000 0005h TLB and L1 cache description7.2.1.1 CPUID Instruction with EAX = 0000 0000hStandard function 0h (EAX = 0) of the CPUID instructionreturns the maximum standard CPUID levels as well asthe processor vendor string.After the instruction is executed, the EAX register containsthe maximum standard CPUID levels supported. Themaximum standard CPUID level is the highest acceptablevalue for the EAX register input. This does not include theextended CPUID levels.The EBX through EDX registers contain the vendor stringof the processor as shown in Table 7-17.Table 7-17. CPUID Data Returned when EAX = 0Register(Note) Returned Contents DescriptionEAX 2 Maximum StandardLevelEBX 69 72 7943 Vendor ID String 1(iryC)EDX 73 6E 4978 Vendor ID String 2(snlx)ECX 64 61 6574 Vendor ID String 3(daet)Note: The register column is intentionally out of order.7.2.1 Standard CPUID LevelsThe standard CPUID levels are part of the standard x86instruction set.www.national.com 212 Revision 1.3