Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesSignal Definitions (Continued)2.2.4 Video Interface Signals (Continued)Signal NameFP_HSYNC L2 R4 O Flat Panel Horizontal SyncFlat Panel Horizontal Sync establishes the line rate and horizontalretrace interval for a TFT display. Polarity is programmable.(See Table 4-31 on page 146 for programming information.)This signal is an input to the CS5530. The CS5530 re-drives thissignal to the flat panel.If no flat panel is used in the system, this signal is not connected.FP_VSYNC J1 P2 O Flat Panel Vertical SyncFlat Panel Vertical Sync establishes the screen refresh rate andvertical retrace interval for a TFT display. Polarity is programmable.(See Table 4-31 on page 146 for programming information.)This signal is an input to the CS5530. The CS5530 re-drives thissignal to the flat panel.If no flat panel is used in the system, this signal is not connected.ENA_DISP AD5 AM6 O Display EnableDisplay Enable indicates the active display portion of a scan lineto the CS5530.In a CS5530-based system, this signal is required to be connected.VID_RDY AD1 AK2 I Video ReadyThis input signal indicates that the video FIFO in the CS5530 isready to receive more data.VID_VAL M2 S3 O Video ValidVID_VAL indicates that video data to the CS5530 is valid.VID_DATA[7:0] Refer Refer O Video Data Busto toWhen the Video Port is enabled, this bus drives Video (YUV orTable 2-3 Table 2-5RGB 5:6:5) data synchronous to the VID_CLK output.PIXEL[17:0]BGAPin NoRefertoTable 2-3SPGAPin No Type DescriptionRefertoTable 2-5OGraphics Pixel Data BusThis bus drives graphics pixel data synchronous to the PCLKoutput.www.national.com 38 Revision 1.3
Signal Definitions (Continued)2.2.5 Power, Ground, and No Connect SignalsSignal NameVSSVCC2VCC3BGAPin No.RefertoTable 2-3(Total of71)RefertoTable 2-3(Total of32)RefertoTable 2-3(Total of32)NC D26,E24,AC5SPGAPin No. Type DescriptionRefertoTable 2-5(Total of50)RefertoTable 2-5(Total of32)RefertoTable 2-5(Total of18)E37,F36, Q5,X2, Z2,AM36GNDPWRPWRGround Connection2.2V, 2.5V, or 2.9V (Nominal) Core Power Connection3.3V (Nominal) I/O Power ConnectionNo ConnectionA line designated as NC must be left disconnected.Geode GXLV Processor Series2.2.6 Internal Test and Measurement SignalsSignal NameBGAPin No.SPGAPin No. Type DescriptionFLT# AC2 AJ3 I FloatFloat forces the GXLV processor to float all outputs in the highimpedancestate and to enter a power-down state.RW_CLK AE6 AL11 O Raw ClockThis output is the GXLV processor clock. This debug signal canbe used to verify clock operation.TEST[3:0] B22,A23,B21,C21TCLKJ2(PU)D28,B32,D26,A33P4(PU)OISDRAM Test OutputsThese outputs are used for internal debug only.Test ClockJTAG test clock.This pin is internally connected to a weak (>20-kohm) pull-upresistor.TDID2(PU)F4(PU)I Test Data InputJTAG serial test-data input.This pin is internally connected to a weak (>20-kohm) pull-upresistor.TDO F1 J1 O Test Data OutputJTAG serial test-data output.Revision 1.3 39 www.national.com
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Instruction Set (Continued)7.5 MMX
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Geode GXLV Processor Series Low Pow
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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