Geode GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)ACT — The activate command is used to open a row in aparticular bank for a subsequent access. The value on theBA lines selects the bank, and the address on the MAlines selects the row. This row remains open for accessesuntil a precharge command is issued to that bank. A prechargecommand must be issued before opening a differentrow in the same bank.WRT — The write command is used to initiate a burstwriteaccesstoanactiverow.ThevalueontheBAlinesselect the component bank, and the address provided bythe MA lines select the starting column location. Thememory controller does not perform auto precharge duringwrite operations. This leaves the page open for subsequentaccesses. Data appearing on the MD lines iswritten to the DQM logic level appearing coincident withthe data. If the DQM signal is registered low, the correspondingdata will be written to memory. If the DQM isdriven high, the corresponding data will be ignored, and awrite will not be executed to that location.READ —Thereadcommandisusedtoinitiateaburstread access to an active row. The value on the BA linesselect the component bank, and the address provided bythe MA lines select the starting column location. Thememory controller does not perform auto precharge duringread operations. Valid data-out from the starting columnaddress is available following the CAS latency afterthe read command. The DQM signals are asserted lowduring read operations.RFSH — Auto refresh is used during normal operationand is analogous to the CAS-before-RAS (CBR) refresh inconventional DRAMs. During auto refresh the addressbits are “don’t care”. The memory controller prechargesall banks prior to an auto refresh cycle. Auto refreshcycles are issued approximately 15 µs apart.The self refresh command is used to retain data in theSDRAMs even when the rest of the system is powereddown. The self refresh command is similar to an autorefresh command except CKE is disabled (low). Thememory controller issues a self refresh command during3V Suspend mode when all the internal clocks arestopped.4.3.3.1 SDRAM Initialization SequenceAfter the clocks have started and stabilized, the memorycontroller SDRAM initialization sequence begins:1) Precharge all component banks2) Perform eight refresh cycles3) Perform an MRS cycle4) Perform eight refresh cyclesThis sequence is compatible with the majority of SDRAMsavailable from the various vendors.Geode GXLV Processor SeriesRevision 1.3 111 www.national.com