Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesIntegrated Functions (Continued)Table 4-29. Display Controller Configuration and Status Registers (Continued)Bit Name Description15 PXDB Pixel Double: Allow pixel doubling to stretch the displayed image in the horizontal dimension:0 = Disable; 1 = Enable.If bit 15 is enabled, timing parameters should be programmed as if no pixel doubling is used, however, theframe buffer should be loaded with half the normal pixels per line. Also, the FB_LINE_SIZE parameter inDC_BUF_SIZE should be set for the number of bytes to be transferred for the line rather than the numberdisplayed.14 INTL Interlace Scan: Allow interlaced scan mode:0 = Disable (Non-interlaced scanning is supported.)1 = Enable (If a flat panel is attached, it should be powered down before setting this bit.)13 PLNR VGA Planar Mode: This bit must be set high for all VGA planar display modes.12 FCEN Flat Panel Center: Allows the border and active portions of a scan line to be qualified as “active” to a flatpanel display via the ENADISP signal. This allows the use of a large border region for centering the flatpanel display. 0 = Disable; 1 = Enable.When disabled, only the normal active portion of the scan line will be qualified as active.11 FVSP Flat Panel Vertical Sync Polarity:0 = Causes TFT vertical sync signal to be normally low, generating a high pulse during sync interval.1 = Causes TFT vertical sync signal to be normally high, generating a low pulse during sync interval.10 FHSP Flat Panel Horizontal Sync Polarity:0 = Causes TFT horizontal sync signal to be normally low, generating a high pulse during sync interval.1 = Causes TFT horizontal sync signal to be normally high, generating a low pulse during sync interval.9 CVSP CRT Vertical Sync Polarity:0 = Causes CRT_VSYNC signal to be normally low, generating a high pulse during the retrace interval.1 = Cause CRT_VSYNC signal to be normally high, generating a low pulse during the retrace interval.8 CHSP CRT Horizontal Sync Polarity:0 = Causes CRT_HSYNC signal to be normally low, generating a high pulse during the retrace interval.1 = Causes CRT_HSYNC signal to be normally high, generating a low pulse during the retrace interval.7 BLNK Blink Enable: Blink circuitry: 0 = Disable; 1 = Enable.If enabled, the hardware cursor will blink as well as any pixels. This is provided to maintain compatibilitywith VGA text modes. The blink rate is determined by the bit 16 (BKRT).6 VIEN Vertical Interrupt Enable: Generate a vertical interrupt on the occurrence of the next vertical sync pulse:0 = Disable, vertical interrupt is cleared;1 = Enable.This bit is provided to maintain backward compatibility with the VGA.5 TGEN Timing Generator Enable: Allow timing generator to generate the timing control signals for the display.0 = Disable, the Timing Registers may be reprogrammed, and all circuitry operating on the DCLK will bereset.1 = Enable, no write operations are permitted to the Timing Registers.4 DDCK DDC Clock: This bit is used to provide the serial clock for reading the DDC data pin. This bit is multiplexedonto the CRT_VSYNC pin, but in order for it to have an effect, the VSYE bit[2] must be set low to disablethe normal vertical sync. Software should then pulse this bit high and low to clock data into the GXLV processor.This feature is provided to allow support for the VESA Display Data Channel standard level DDC1.3 BLKE Blank Enable: Allow generation of the composite blank signal to the display device:0 = Disable; 1 = Enable.When disabled, the ENA_DISP output will be a static low level. This allows VESA DPMS compliance.2 HSYE Horizontal Sync Enable: Allow generation of the horizontal sync signal to a CRT display device:0 = Disable; 1 = Enable.When disabled, the HSYNC output will be a static low level. This allows VESA DPMS compliance.Note that this bit only applies to the CRT; the flat panel HSYNC is controlled by the automatic powersequencing logic.www.national.com 146 Revision 1.3
Integrated Functions (Continued)Table 4-29. Display Controller Configuration and Status Registers (Continued)Bit Name Description1 VSYE Vertical Sync Enable: Allow generation of the vertical sync signal to a CRT display device:0 = Disable; 1 = Enable.When disabled, the VSYNC output will be a static low level. This allows VESA DPMS compliance.Note that this bit only applies to the CRT; the flat panel VSYNC is controlled by the automatic powersequencing logic.0 PPE Pixel Port Enable: On a low-to-high transition this bit will enable the pixel port outputs.On a high-to-low transition, this bit will disable the pixel port outputs.GX_BASE+830Ch-830Fh DC_OUTPUT_CFG Register (R/W) (Locked) Default Value = xxx00000h31:16 RSVD Reserved: Set to 0.15 DIAG Compressed Line Buffer Diagnostic Mode: This bit allows testability of the Compressed Line Buffer viathe diagnostic access registers. A low-to-high transition resets the Compressed Line Buffer write pointer. 0= Disable (Normal operation); 1 = Enable.14 CFRW Compressed Line Buffer Read/Write Select: Enables the read/write address to the Compressed LineBuffer for use in diagnostic testing of the RAM.0 = Write address enabled1 = Read address enabled13 PDEH PixelDataEnableHigh:0 = The PIXEL [17:9] data bus to be driven to a logic low level.12 PDEL Panel Data Enable Low:0 = This bit will cause the PIXEL[8:0] data bus to be driven to a logic low level.11:8 RSVD Reserved: Set to 0.7:5 RSVD Reserved: Set to 0.4:3 RSVD Reserved: Set to 0.2 PCKE PCLK Enable:0 = PCLK is disabled and a low logic level is driven off-chip.1 = Enable PCLK to be driven off-chip.1 16FMT 16-bpp Format: Selects RGB display mode:0 = RGB 5-6-5 mode1 = RGB 5-5-5 display modeThis bit is only significant if 8-bpp (OUTPUT_CONFIG, bit 0) is low, indicating 16-bpp mode.0 8-bpp 8-bpp / 16-bpp Select:0 = 16-bpp display mode is selected. 16FMT (OUTPUT_CONFIG, bit 1) will indicate the format of the 16-bit data.)1 = 8-bpp display mode is selected. Used in VGA emulation.Geode GXLV Processor SeriesRevision 1.3 147 www.national.com
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Geode GXLV Processor Series Low Pow
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