Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesProcessor Programming (Continued)Single-step operation is enabled by setting the TF bit (bit8) in the EFLAGS register. When the TF is set, the CPUgenerates a debug exception (vector 1) after the executionof every instruction. Data breakpoints also generate adebug exception and are specified by loading the debugregisters (DR0-DR3, see Table 3-12 on page 55) with theappropriate values.A Fault exception is reported before completion of theinstruction that generated the exception. By reporting thefault before instruction completion, the CPU is left in astate that allows the instruction to be restarted and theeffects of the faulting instruction to be nullified. Faultexceptions include divide-by-zero errors, invalid opcodes,page faults and coprocessor errors. Debug exceptions(vector 1) are also handled as faults (except for databreakpoints and single-step operations). After executionof the fault service routine, the instruction pointer points tothe instruction that caused the fault.An Abort exception isatypeoffaultexceptionthatissevere enough that the CPU cannot restart the program atthe faulting instruction. The double fault (vector 8) is theonly abort exception that occurs on the CPU.3.6.3 Interrupt VectorsWhen the CPU services an interrupt or exception, the currentprogram’s instruction pointer and flags are pushedonto the stack to allow resumption of execution of theinterrupted program. In protected mode, the processoralso saves an error code for some exceptions. Programcontrol is then transferred to the interrupt handler (alsocalled the interrupt service routine). Upon execution of anIRET at the end of the service routine, program executionresumes at the instruction pointer address saved on thestack when the interrupt was serviced.3.6.3.1 Interrupt Vector AssignmentsEach interrupt (except SMI#) and exception are assignedone of 256 interrupt vector numbers as shown in Table 3-29. The first 32 interrupt vector assignments are definedor reserved. INT instructions acting as software interruptsmay use any of interrupt vectors, 0 through 255.The non-maskable hardware interrupt (NMI) is assignedvector 2. Illegal opcodes including faulty FPU instructionswill cause an illegal opcode exception, interrupt vector 6.NMI interrupts are enabled by setting bit 2 of the CCR7register(IndexEBh[2]=1,seeTable3-11onpage52forregister format).In response to a maskable hardware interrupt (INTR), theCPU issues interrupt acknowledge bus cycles used to readthe vector number from external hardware. These vectorsshould be in the range 32 to 255 as vectors 0 to 31 are predefined.3.6.3.2 Interrupt Descriptor TableThe interrupt vector number is used by the CPU to locatean entry in the interrupt descriptor table (IDT). In realmode, each IDT entry consists of a 4-byte far pointer tothe beginning of the corresponding interrupt service routine.In protected mode, each IDT entry is an 8-bytedescriptor. The Interrupt Descriptor Table Register (IDTR)specifies the beginning address and limit of the IDT. FollowingRESET, the IDTR contains a base address of00000000h with a limit of 3FFh.The IDT can be located anywhere in physical memory asdetermined by the IDTR register. The IDT may contain differenttypes of descriptors: interrupt gates, trap gates andtask gates. Interrupt gates are used primarily to enter ahardware interrupt handler. Trap gates are generally usedto enter an exception handler or software interrupt handler.If an interrupt gate is used, the Interrupt Enable Flag(IF) in the EFLAGS register is cleared before the interrupthandler is entered. Task gates are used to make the transitionto a new task.Table 3-29. Interrupt Vector AssignmentsInterruptVectorFunctionExceptionType0 Divide error Fault1 Debug exception Trap/Fault*2 NMI interrupt ---3 Breakpoint Trap4 Interrupt on overflow Trap5 BOUND range exceeded Fault6 Invalid opcode Fault7 Device not available Fault8 Double fault Abort9 Reserved ---10 Invalid TSS Fault11 Segment not present Fault12 Stack fault Fault13 General protection fault Trap/Fault14 Page fault Fault15 Reserved ---16 FPU error Fault17 Alignment check exception Fault18:31 Reserved ---32:55 Maskable hardware interrupts Trap0:255 Programmed interrupt TrapNote: *Data breakpoints and single steps are traps. All otherdebug exceptions are faults.www.national.com 80 Revision 1.3
Processor Programming (Continued)3.6.4 Interrupt and Exception PrioritiesAs the CPU executes instructions, it follows a consistentpolicy for prioritizing exceptions and hardware interrupts.The priorities for competing interrupts and exceptions arelisted in Table 3-30. SMM interrupts always take precedence.Debug traps for the previous instruction and nextinstructions are handled as the next priority. When NMIand maskable INTR interrupts are both detected at thesame instruction boundary, the GXLV processor servicesthe NMI interrupt first.The CPU checks for exceptions in parallel with instructiondecoding and execution. Several exceptions can resultfrom a single instruction. However, only one exception isgenerated upon each attempt to execute the instruction.Each exception service routine should make the appropriatecorrections to the instruction and then restart theinstruction. In this way, exceptions can be serviced untilthe instruction executes properly.The CPU supports instruction restart after all faults,except when an instruction causes a task switch to a taskwhose Task State Segment (TSS) is partially not present.A TSS can be partially not present if the TSS is not pagealigned and one of the pages where the TSS resides isnot currently in memory.Geode GXLV Processor SeriesTable 3-30. Interrupt and Exception PrioritiesPriority Description Notes0 Reset. Caused by the assertion of RESET.1 SMM hardware interrupt. SMM interrupts are caused by SMI# asserted and always havehighest priority.2 Debug traps and faults from previous instruction. Includes single-step trap and data breakpoints specified in thedebug registers.3 Debug traps for next instruction. Includes instruction execution breakpoints specified in the debugregisters.4 Non-maskable hardware interrupt. Caused by NMI asserted.5 Maskable hardware interrupt. Caused by INTR asserted and IF = 1.6 Faults resulting from fetching the next instruction. Includes segment not present, general protection fault and pagefault.7 Faults resulting from instruction decoding. Includes illegal opcode, instruction too long, or privilege violation.8 WAIT instruction and TS = 1 and MP = 1. Device not available exception generated.9 ESC instruction and EM = 1 or TS = 1. Device not available exception generated.10 Floating point error exception. Caused by unmasked floating point exception with NE = 1.11 Segmentation faults (for each memory referencerequired by the instruction) that prevent transferringthe entire memory operand.12 Page Faults that prevent transferring the entirememory operand.13 Alignment check fault.Includes segment not present, stack fault, and general protectionfault.Revision 1.3 81 www.national.com
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Geode GXLV Processor Series Low Pow
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