Geode GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)Bit Name Description13 RSVD Reserved: Set to 0.12 DIMM0_COMP_BNKTable 4-15. Memory Controller Registers (Continued)DIMM0 Component Banks (Banks 0 and 1): Selects the number of component banks per modulebank for DIMM0:0 = 2 Component banks1 = 4 Component banksBanks 0 and 1 must have the same number of component banks.11 RSVD Reserved: Set to 0.10:8 DIMM0_SZ DIMM0Size(Banks0and1):Selects the size of DIMM1:000 = 4 MB 010 = 16 MB 100 = 64 MB 110 = 256 MB001 = 8 MB 011 = 32 MB 101 = 128 MB 111 = 512 MB (not supported)This size is the total of both banks 0 and 1. Also, banks 0 and 1 must be the same size.7 RSVD Reserved: Set to 0.6:4 DIMM0_PG_SZ DIMM0PageSize(Banks0and1):Selects the page size of DIMM0:000 = 1 KB 010 = 4 KB 1xx = 16 KB001 = 2 KB 011 = 8 KB 111 = DIMM0 not installedBoth banks 0 and 1 must have the same page size. When DIMM0 (neither bank 0 or 1) is not installed,program all other DIMM0 fields to 0.3:0 RSVD Reserved: Set to 0.Geode GXLV Processor SeriesGX_BASE+840Ch-840Fh MC_SYNC_TIM1 (R/W) Default Value = 2A733225h31 RSVD Reserved: Set to 0.30:28 LTMODE CAS Latency (LTMODE): CAS latency is the delay, in SDRAM clock cycles, between the registrationof a read command and the availability of the first piece of output data. This parameter significantlyaffects system performance. Optimal setting should be used. If DIMMs are used BIOS can interrogateEEPROM across the I 2 C interface to determine this value:000 = Reserved 010 = 2 CLK 100 = 4 CLK 110 = 6 CLK001 = Reserved 011 = 3 CLK 101 = 5 CLK 111 = 7 CLKThis field will not take effect until SDRAMPRG (bit 0 of MC_MEM_CNTRL1) transitions from 0 to 1.27:24 RC RFSH to RFSH/ACT Command Period (tRC): Minimum number of SDRAM clock between RFSHand RFSH/ACT commands:0000 = Reserved 0100 = 5 CLK 1000 = 9 CLK 1100 = 13 CLK0001 = 2 CLK 0101 = 6 CLK 1001 = 10 CLK 1101 = 14 CLK0010 = 3 CLK 0110 = 7 CLK 1010 = 11 CLK 1110 = 15 CLK0011 = 4 CLK 0111 = 8 CLK 1011 = 12 CLK 1111 = 16 CLK23:20 RAS ACT to PRE Command Period (tRAS): Minimum number of SDRAM clocks between ACT and PREcommands:0000 = Reserved 0100 = 5 CLK 1000 = 9 CLK 1100 = 13 CLK0001 = 2 CLK 0101 = 6 CLK 1001 = 10 CLK 1101 = 14 CLK0010 = 3 CLK 0110 = 7 CLK 1010 = 11 CLK 1110 = 15 CLK0011 = 4 CLK 0111 = 8 CLK 1011 = 12 CLK 1111 = 16 CLK19 RSVD Reserved: Set to 0.18:16 RP PRE to ACT Command Period (tRP): Minimum number of SDRAM clocks between PRE and ACTcommands:000 = Reserved 010 = 2 CLK 100 = 4 CLK 110 = 6 CLK001 = 1 CLK 011 = 3 CLK 101 = 5 CLK 111 = 7 CLK15 RSVD Reserved: Set to 0.14:12 RCD Delay Time ACT to READ/WRT Command (tRCD): Minimum number of SDRAM clock between ACTand READ/WRT commands. This parameter significantly affects system performance. Optimal settingshould be used:000 = Reserved 010 = 2 CLK 100 = 4 CLK 110 = 6 CLK001 = 1 CLK 011 = 3 CLK 101 = 5 CLK 111 = 7 CLK11 RSVD Reserved: Set to 0.10:8 RRD ACT(0) to ACT(1) Command Period (tRRD): Minimum number of SDRAM clocks between ACT andACT command to two different component banks within the same module bank. The memory controllerdoes not perform back-to-back Activate commands to two different component banks without aREAD or WRT command between them. Hence, this field should be set to 001.Revision 1.3 115 www.national.com