Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesPower Management (Continued)5.2 SUSPEND MODES AND BUS CYCLESThe following subsections describe the bus cycles of thevarious suspend states.5.2.1 Timing Diagram for Suspend-on-HaltThe CPU enters Suspend-on-Halt as a result of executinga halt (HLT) instruction if the SUSP_HALT bit in CCR2(Index C2h[3]) is set. When the HLT instruction is executed,the halt PCI cycle is run on the PCI bus normallyand then the SUSPA# pin will go active to indicate that theprocessor has entered the suspend state. This state isslightly is different from CPU Suspend because of howSuspend-on-Halt is entered and how it is exited. Suspendon-Haltis exited upon recognition of an unmasked INTRor an SMI#. Normally SUSPA# is deactivated within sixSYSCLKS from the detection of an active interrupt. However,the deactivation of SUSPA# may be delayed until theend of an active refresh cycle.The CPU allows PCI master accesses during a HALT-initiatedSuspend mode. The SUSPA# pin will go inactive duringthe duration of the PCI activity. If the CPU is in themiddle of a PCI master access when the Halt instruction isexecuted, the assertion of SUSPA# will be delayed untilthe PCI access is completed. See Figure 5-1 for timingdetails.PCI HALT CYCLESYSCLKFRAME#C/BE[3:0]#IOXAD[15:0]XIXIRDY#INTR, SMI#SUSPA#Figure 5-1. HALT-Initiated Suspend Modewww.national.com 178 Revision 1.3
Power Management (Continued)5.2.2 Initiating Suspend with SUSP#The GXLV processor enters the Suspend mode inresponse to SUSP# input assertion only when certainconditions are met. First, the USE_SUSP bit must be setin CCR2 (Index C2h[7]). In addition, execution of the currentinstructions and any pending decoded instructionsand associated bus cycles must be completed. SUSP# issampled on the rising edge of SYSCLK, and must meetspecified setup and hold times to be recognized at a particularSYSCLK edge. See Figure 5-2 for timing details.When all conditions are met, the SUSPA# output isasserted. The time from assertion of SUSP# to the activationof SUSPA# depends on which instructions weredecoded prior to assertion of SUSP#. Normally, onceSUSP# has been sampled inactive the SUSPA# outputwill be deactivated within two clocks. However, the deactivationof SUSPA# may be delayed until the end of anactive refresh cycle.If the CPU is already in a Suspend mode initiated bySUSP#, one occurrence of INTR and SMI# is stored forexecution after Suspend mode is exited. The CPU alsoallows PCI master accesses during a SUSP#-initiatedSuspendmode.SeeFigure5-3fortimingdetails.Ifanunmasked REQx# is asserted, the GXLV processor willdeassert SUSPA# and exit Suspend mode to respond tothe PCI master access. If SUSP# is asserted when thePCI master access is completed, REQx# deasserted, theGXLV processor will reassert SUSPA# and return to aSUSP#-initiated Suspend mode. If the CPU is in the middleof a PCI master access when SUSP# is asserted, theassertion of SUSPA# will be delayed until the PCI accessis completed.Geode GXLV Processor SeriesSYSCLKSUSP#SUSPA#Figure 5-2. SUSP#-Initiated Suspend ModeSYSCLKREQx#FRAME#TRDY#SUSP#SUSPA#Figure 5-3. PCI Access During Suspend ModeRevision 1.3 179 www.national.com
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Geode GXLV Processor Series Low Pow
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