Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesProcessor Programming (Continued)Gate DescriptorsFour kinds of gate descriptors are used to provide protectionduring control transfers:• Call gates• Trap gates• Interrupt gates• Task gates(For more information on protection refer to Section 3.9“Protection” on page 91.)Call Gate Descriptor (CGD). Call gates are used todefine legal entry points to a procedure with a higher privilegelevel. The call gates are used by CALL and JUMPinstructions in much the same manner as code segmentdescriptors. When a decoded instruction refers to a callgate descriptor in the GDT or LDT, the call gate is used topoint to another descriptor in the table that defines thedestination code segment.The following privilege levels are tested during the transferthrough the call gate:• CPL = Current Privilege Level• RPL = Segment Selector Field• DPL = Descriptor Privilege Level in the call gatedescriptor• DPL = Descriptor Privilege Level in the destinationcode segmentThe maximum value of the CPL and RPL must be equalor less than the gate DPL. For a JMP instruction the destinationDPL equals the CPL. For a CALL instruction thedestination DPL is less than or equal to the CPL.Conforming Code Segments. Transfer to a procedurewith a higher privilege level can also be accomplished bybypassing the use of call gates, if the requested procedureis to be executed in a conforming code segment.Conforming code segments have the C bit set in theTYPE field in their descriptor.The bit structure and definitions for gate descriptors areshown in Tables 3-24 and 3-25.Table 3-24. Gate Descriptors31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Memory Offset +4OFFSET[31:16] P DPL 0 TYPE 0 0 0 PARAMETERSMemory Offset +0SELECTOR[15:0]OFFSET[15:0]Table 3-25. Gate Descriptors Bit DefinitionsBitMemoryOffset Name Description31:16 +4 OFFSET Offset: Offset used during a call gate to calculate the branch target.15:0 +031:16 +0 SELECTOR Segment Selector15 +4 P Segment Present14:13 +4 DPL Descriptor Privilege Level11:8 +4 TYPE Segment Type:0100 = 16-bit call gate 1100 = 32-bit call gate0101 = Task gate 1110 = 32-bit interrupt gate0110 = 16-bit interrupt gate 1111 = 32-bit trap gate0111 = 16-bit trap gate4:0 +4 PARAMETERS Parameters: Number of parameters to copy from the caller’s stack to the called procedure’sstack.www.national.com 74 Revision 1.3
Processor Programming (Continued)Task State Segments DescriptorsThe CPU enables rapid task switching using JMP andCALL instructions that refer to Task State Segment (TSS)descriptors. During a switch, the complete task state ofthe current task is stored in its TSS, and the task state ofthe requested task is loaded from its TSS. The TSSs aredefined through special segment descriptors and gates.The Task Register (TR) holds 16-bit descriptors that containthe base address and segment limit for each taskstate segment. The TR is loaded and stored via the LTRand STR instructions, respectively. The TR can beaccessed only during protected mode and can be loadedwhen the privilege level is 0 (most privileged). When theTR is loaded, the TR selector field indexes a TSS descriptorthat must reside in the Global Descriptor Table (GDT).Only the 16-bit selector of a TSS descriptor in the TR isaccessible. The BASE, TSS LIMIT and ACCESS RIGHTfields are program invisible.During task switching, the processor saves the currentCPU state in the TSS before starting a new task. The TSScan be either a 386/486-type 32-bit TSS (see Table 3-26) or a286-type 16-bit TSS (see Table 3-27).Task Gate Descriptors. A task gate descriptor providescontrolled access to the descriptor for a task switch. TheDPL of the task gate is used to control access. The selector’sRPL and the CPL of the procedure must be a higherlevel (numerically less) than the DPL of the descriptor.The RPL in the task gate is not used.TheI/OMapBaseAddressfieldinthe32-bitTSSpointsto an I/O permission bit map that often follows the TSS atlocation +68h.Geode GXLV Processor SeriesTable 3-26. 32-Bit Task State Segment (TSS) Table31 16 15 0I/O Map Base Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T +64h0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Selector for Task’s LDT +60h0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GS +5Ch0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FS +58h0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DS +54h0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS +50h0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CS +4Ch0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ES +48hEDI +44hESI +40hEBP+3ChESP +38hEBX +34hEDX +30hECX+2ChEAX +28hEFLAGS +24hEIP +20hCR3+1Ch0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS for CPL = 2 +18hESP for CPL = 2 +14h0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS for CPL = 1 +10hESP for CPL = 1+Ch0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS for CPL = 0 +8hESP for CPL = 0 +4h0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Back Link (Old TSS Selector) +0hNote: 0=ReservedRevision 1.3 75 www.national.com
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Geode GXLV Processor Series Low Pow
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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