Geode GXLV Processor Series Low Power Integrated x86 Solutions

7.0 Instruction SetThis section summarizes the Geode GXLV processorinstruction set and provides detailed information on theinstruction encodings. The instruction set is divided intofour categories:• Processor Core Instruction Set - listed in Table 7-27 onpage 217.• FPU Instruction Set - listed in Table 7-29 on page 229.• MMX Instruction Set - listed in Table 7-31 on page 234.• ExtendedMMXInstructionSet-listedinTable7-33onpage 239.These tables provide information on the instruction encoding,and the instruction clock counts for each instruction.The clock count values for these tables are based on thefollowing assumptionscalculation uses two general register components,add one clock to the clock count shown.7. All clock counts assume aligned 32-bit memory/IOoperands.8. If instructions access a 32-bit operand on oddaddresses, add one clock for read or write and addtwo clocks for read and write.9. For non-cached memory accesses, add two clocks(clock doubled GXLV processor cores) or four clocks(clock tripled GXLV processor cores), assuming zerowait state memory accesses.10. Locked cycles are not cacheable. Therefore, using theLOCK prefix with an instruction adds additional clocksas specified in item 9 above.Geode GXLV Processor Series1. All clock counts refer to the internal processor coreclock frequency. For example, clock doubled GXLVprocessor cores will reference a clock frequency thatis twice the bus frequency.2. The instruction has been prefetched, decoded and isready for execution.3. Bus cycles do not require wait states.4. There are no local bus HOLD requests delayingprocessor access to the bus.5. No exceptions are detected during instruction execution.6. If an effective address is calculated, it does not usetwo general register components. One register,scaling and displacement can be used within theclock count shown. However, if the effective address7.1 GENERAL INSTRUCTION SET FORMATDepending on the instruction, the GXLV processor coreinstructions follow the general instruction format shown inTable 7-1.These instructions vary in length and can start at any byteaddress. An instruction consists of one or more bytes thatcan include prefix bytes, at least one opcode byte, a modr/m byte, an s-i-b byte, address displacement, and immediatedata. An instruction can be as short as one byte andas long as 15 bytes. If there are more than 15 bytes in theinstruction, a general protection fault (error code 0) is generated.The fields in the general instruction format at the bytelevel are summarized in Table 7-2 and detailed in the followingsubsections.Table 7-1. General Instruction Set FormatRegister and Address Mode SpecifierPrefix (optional)Opcodemod r/m Bytes-i-b Bytemod reg r/m ss index baseAddressDisplacementImmediateData0 or More Bytes 1 or 2 Bytes 7:6 5:3 2:0 7:6 5:3 2:0 0, 8, 16, or 32 Bits 0, 8, 16, or 32 BitsTable 7-2. Instruction FieldsField NamePrefix (optional)Opcodemodregr/mssindexbaseAddress DisplacementImmediate DataDescriptionPrefix Field(s): One or more optional fields that are used to specify segment register override, addressand operand size, repeat elements in string instruction, LOCK# assertion.Opcode Field: Identifies instruction operation.Address Mode Specifier: Used with r/m field to select addressing mode.General Register Specifier: Uses reg, sreg3 or sreg2 encoding depending on opcode field.Address Mode Specifier: Used with mod field to select addressing mode.Scale factor: Determines scaled-index address mode.Index: Determines general register to be used as index register.Base: Determines general register to be used as base register.Displacement: Determines address displacement.Immediate Data: Immediate data operand used by instruction.Revision 1.3 207 www.national.com