Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesProcessor Programming (Continued)3.7.6 SMM Memory SpaceSMM memory space is defined by specifying the baseaddress and size of the SMM memory space in the SMARregister. The base address must be a multiple of the SMMmemory space size. For example, a 32 KB SMM memoryspace must be located at a 32 KB address boundary. Thememory space size can range from 4 KB to 32 MB. Executionof the interrupt begins at the base of the SMM memoryspace.SMM memory space accesses are always cacheable,which allows SMM routines to run faster.3.7.7 SMI Generation for Virtual VGAThe GXLV processor implements SMI generation for VGAaccesses. When enabled memory write operations inregions A0000h to AFFFFh, B0000h to B7FFFh, andB8000h to BFFFFh generate an SMI. Memory reads arenot trapped by the GXLV processor. When enabled, theGXLV processor traps I/O addresses for VGA in the followingregions: 3B0h to 3BFh, 3C0h to 3CFh, and 3D0hto 3DFh. Memory-write trapping is performed duringinstruction decode in the processor core. I/O read andwrite trapping is implemented in the Internal Bus InterfaceUnit of the GXLV processor.The SMI-generation hardware requires two additionalconfiguration registers to control and mask SMI interruptsin the VGA memory space: VGACTL and VGAM. TheVGACTL register has a control bit for each address rangeshown above. The VGAM register has 32 bits that canselectively disable 2 KB regions within the VGA memory.The VGAM applies only to the A0000h to AFFFFh region.If this region is not enabled in VGA_CTL, then the contentsof VGAM is ignored. The purpose of VGAM is to preventan SMI from occurring when non-displayed VGAmemory is accessed. This is an enhancement whichimproves performance for double-buffered applications.The format of each register is shown in Table 4-37 onpage 163.3.7.8 SMM Service Routine ExecutionUpon entry into SMM, after the SMM header has beensaved, the CR0, EFLAGS, and DR7 registers are set totheir reset values. The Code Segment (CS) register isloaded with the base, as defined by the SMAR register,and a limit of 4 GB. The SMM service routine then beginsexecution at the SMM base address in real mode.The programmer must save, restore the value of any registersnot saved in the header that may be changed by theSMM service routine. For data accesses immediately afterentering the SMM service routine, the programmer mustuse CS as a segment override. I/O port access is possibleduring the routine but care must be taken to save registersmodified by the I/O instructions. Before using a segmentregister, the register and the register’s descriptor cache contentsshould be saved using the SVDC instruction.Hardware interrupts, INTRs and NMIs, may be servicedduring an SMM service routine. If interrupts are to be servicedwhile executing in the SMM memory space, theSMM memory space must be within the address range of0 to 1 MB to guarantee proper return to the SMM serviceroutine after handling the interrupt.INTRs are automatically disabled when entering SMMsince the IF flag (EFLAGS register, bit 9) is set to its resetvalue. Once in SMM, the INTR can be enabled by settingthe IF flag. An NMI event in SMM can be enabled by settingNMI_EN high in the CCR3 register (Index C3h[1]). IfNMI is not enabled while in SMM, the CPU latches oneNMI event and services the interrupt after NMI has beenenabled or after exiting SMM through the RSM instruction.Upon entering SMM, the processor is in real mode, but itmay exit to either real or protected mode depending on itsstate when SMM was initiated. The SMM header indicatesto which state it will exit.WithintheSMMserviceroutine,protectedmodemaybeentered and exited as required, and real or protectedmode device drivers may be called.To exit the SMM service routine, an RSM instruction,rather than an IRET, is executed. The RSM instructioncauses the GXLV processor core to restore the CPU stateusing the SMM header information and resume executionat the interrupted point. If the full CPU state was saved bythe programmer, the stored values should be reloadedbefore executing the RSM instruction using the MOV,RSDC, RSLDT and RSTS instructions.3.7.8.1 SMI NestingThe SMI mechanism supports nesting of SMI interruptsthrough the SMM service routine the SMI_NEST bit in theCCR4 register (Index E8h[6]), and the Nested SMI Statusbit (bit N in the SMM header, see Table 3-35 "SMM MemorySpace Header Description" on page 86). Nesting is animportant capability in allowing high-priority events, suchas audio virtualization, to interrupt lower-priority SMI codefor VGA virtualization or power management. SMI_NESTcontrols whether SMI interrupts can occur during SMM.SMM service routines can optionally set SMI_NEST highto allow higher-priority SMI interrupts while handling thecurrent event.The SMM service routine is responsible for managing theSMM header data for nested SMI interrupts. The SMMheader must be saved before SMI_NEST is set high, andSMI_NEST must be cleared and its header informationrestored before an RSM instruction is executed.The Nested SMI Status bit has been added to the SMMheader to show whether the current SMI is nested. Theprocessor sets Nested SMI Status high if the processorwas in SMM when the SMI was taken. The processoruses Nested SMI Status on exit to determine whether theprocessor should stay in SMM.www.national.com 88 Revision 1.3
Processor Programming (Continued)When SMI nesting is disabled, the processor holds offexternal SMI interrupts until the currently executing SMMcode exits. When SMI nesting is enabled, the processorcan proceed with the SMI. The SMM service routine willguarantee that no internal SMIs are generated in SMM, sothe processor ignores such events. If the internal andexternal SMI signals are received simultaneously, then theinternal SMI is given priority to avoid losing the event.The state diagram of the SMI_NEST and Nested SMI Statusbits are shown in Figure 3-11 with each stateexplained next.A. When the processor is outside of SMM, Nested SMIStatus is always clear and SMI_NEST is set high.B. The first-level SMI interrupt is received by theprocessor. The microcode clears SMI_NEST, setsNested SMI Status high and saves the previous valueof Nested SMI Status (0) in the SMM header.C. The first-level SMM service routine saves the headerand sets SMI_NEST high to re-enable SMI interruptsfrom SMM.D. A second-level (nested) SMI interrupt is received bythe processor. This SMI is taken even though theprocessor is in SMM because the SMI_NEST bit isset high. The microcode clears SMI_NEST, setsNested SMI Status high and saves the previous valueof Nested SMI Status (1) in the SMM header.E. The second-level SMM service routine saves theheader and sets SMI_NEST to re-enable SMI interruptswithin SMM. Another level of nesting couldoccur during this period.F. The second-level SMM service routine clearsSMI_NEST to disable SMI interrupts, then restores itsSMM header.G. The second-level SMM service routine executes anRSM. The microcode sets SMI_NEST, and restoresthe Nested SMI Status (1) based on the SMMheader.H. The first-level SMM service routine clears SMI_NESTto disable SMI interrupts, then restores its SMMheader.I. The first-level SMM service routine executes anRSM. The microcode sets SMI_NEST high andrestores the Nested SMI Status (0) based on theSMM header.When the processor is outside of SMM, Nested SMI Statusis always clear and SMI_NEST is set high.Geode GXLV Processor SeriesSMI_NESTNested SMI StatusA B C D E F G H IFigure 3-11. SMI Nesting State MachineRevision 1.3 89 www.national.com
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Geode GXLV Processor SeriesArchitec
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Architecture Overview (Continued)Ge
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2.0 Signal DefinitionsThis section
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Signal Definitions (Continued)Index
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Signal Definitions (Continued)PinNo
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Signal Definitions (Continued)Table
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Signal Definitions (Continued)PinNo
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Signal Definitions (Continued)Table
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Signal Definitions (Continued)2.2.2
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Power Management (Continued)CPU Sus
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Electrical Specifications (Continue
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Instruction Set (Continued)JMP Unco
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Instruction Set (Continued)7.5 MMX
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Geode GXLV Processor Series Low Pow
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