Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesProcessor Programming (Continued)Bit Name DescriptionTable 3-15. TR7-TR6 Bit DefinitionsTR7 RegisterTLB Test Data Register (R/W)31:12 PhysicalAddressPhysical Address:TLB lookup: Data field from the TLB.TLB write: Data field written into the TLB.11:10 RSVD Reserved: Set to 0.9:7 TLB LRU LRU Bits:TLB lookup: LRU bits associated with the TLB entry before the TLB lookup.TLB write: Ignored.6:5 RSVD Reserved: Set to 0.4 PL PL Bit:TLB lookup: If PL = 1, read hit occurred. If PL = 0, read miss occurred.TLB write: If PL = 1, REP field is used to select the set. If PL = 0, the pseudo-LRU replacement algorithmis used to select the set.3:2 REP Set Selection:TLB lookup: If PL = 1, this field indicates the set in which the tag was found. If PL = 0, undefined data.TLB write: If PL = 1, this field selects one of the four sets for replacement. If PL = 0, ignored.1:0 RSVD Reserved: Set to 0.TR6 RegisterTLB Test Control Register (R/W)31:12 LinearAddressLinear Address:TLB lookup: The TLB is interrogated per this address. If one and only one match occurs in the TLB, therest of the fields in TR6 and TR7 are updated per the matching TLB entry.TLB write: A TLB entry is allocated to this linear address.11 V Valid Bit:TLB write: If V = 1, the TLB entry contains valid data. If V = 0, target entry is invalidated.10:98:76:5D, D#U, U#R, R#4:1 RSVD Reserved: Set to 0.0 C Command Bit:If C = 1: TLB lookup.If C = 0: TLB write.Dirty Attribute Bit and its Complement (D, D#):User/Supervisor Attribute Bit and its Complement (U, U#):Read/Write Attribute Bit and its Complement (R, R#):Effect on TLB LookupEffect on TLB Write00 = Do not match Undefined01 = Match if D, U, or R bit is a 0 Clear the bit10 = Match if D, U, or R bit is a 1 Set the bit11 = Match if D, U, or R bit is either a 1 or 0 Undefinedwww.national.com 58 Revision 1.3
Processor Programming (Continued)3.3.2.5 Cache Test RegistersThreetestregistersareusedintestingtheprocessor’sonchipcache, TR3-TR5. Table 3-16 is a register map for theCache Test Registers with their bit definitions given in Table3-17 on page 60. The test registers are accessed throughMOV instructions that can be executed only at privilegelevel 0 (real mode is always privilege level 0).The processor’s 16 KB on-chip cache is a four-way setassociative memory that is configured as write-backcache. Each cache set contains 256 entries. Each entryconsists of a 20-bit tag address, a 16-byte data field, avalid bit, and four dirty bits.The 20-bit tag represents the high-order 20 bits of thephysical address. The 16-byte data represents the 16bytes of data currently in memory at the physical addressrepresented by the tag. The valid bit indicates whether thedata bytes in the cache actually contain valid data. Thefour dirty bits indicate if the data bytes in the cache havebeen modified internally without updating external memory(write-back configuration). Each dirty bit indicates thestatus for one DWORD (4 bytes) within the 16-byte datafield.Foreachlineinthecache,therearethreeLRUbitsthatindicate which of the four sets was most recentlyaccessed. A line is selected using bits [11:4] of the physicaladdress. Using a 16-byte cache fill buffer and a 16-byte cache flush buffer, cache reads and writes may beperformed.Figure 3-1 illustrates the internal cache architecture.Geode GXLV Processor SeriesA11-A4DECODELineAddress255254..0Set 0 Set 1 Set 2 Set 3 LRU..........152 --- 0 152 --- 0 152 --- 0 152 --- 0 2 --- 0= Cache Entry (153 bits)Tag Address (20 bits)Data (128 bits)Valid Status (1 bit)Dirty Status (4 bits)Figure 3-1. Cache ArchitectureTable 3-16. Cache Test Registers31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0TR5 Register (R/W)RSVD Line Selection Set/DWORDControlBitsTR4 Register - Cache (R/W)Cache Tag Address 0ValidCacheLRU BitsDirty Bits 0 0 0TR3 Register - Cache (R/W)Cache DataRevision 1.3 59 www.national.com
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Geode GXLV Processor Series Low Pow
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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