Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesInstruction Set (Continued)InstructionTable 7-27. Processor Core Instruction Set Summary (Continued)OpcodeSTD Set Direction Flag FD - 1 - - - - - - - 4 4STI Set Interrupt Flag FB - - 1 - - - - - - 6 6 mSUB Integer SubtractRegister to Register 2 [10dw] [11 reg r/m] x - - - x x x x x 1 1 b hRegister to Memory 2 [100w] [mod reg r/m] 1 1Memory to Register 2 [101w] [mod reg r/m] 1 1Immediate to Register/Memory 8 [00sw] [mod 101 r/m] ### 1 1Immediate to Accumulator (short form) 2 [110w] ### 1 1SVDC Save Segment Register and Descriptor 0F 78 [mod sreg3 r/m] - - - - - - - - - 20 20 s sSVLDT Save LDTR and Descriptor 0F 7A [mod 000 r/m] - - - - - - - - - 20 20 s sSVTS Save TSR and Descriptor 0F 7C [mod 000 r/m] - - - - - - - - - 21 21 s sTEST Test BitsRegister/Memory and Register 8 [010w] [mod reg r/m] 0 - - - x x u x 0 1 1 b hImmediate Data and Register/Memory F [011w] [mod 000 r/m] ### 1 1Immediate Data and Accumulator A [100w] ### 1 1VERR Verify Read AccessTo Register/Memory 0F 00 [mod 100 r/m] - - - - - x - - - 8 a g,h,j,pVERW Verify Write AccessTo Register/Memory 0F 00 [mod 101 r/m] - - - - - x - - - 8 a g,h,j,pWAIT Wait Until FPU Not Busy 9B - - - - - - - - - 1 1WBINVD Write-Back and Invalidate Cache 0F 09 - - - - - - - - - 23 23 t tWRMSR Write to Model Specific Register 0F 30 - - - - - - - - -XADD Exchange and AddRegister1, Register2 0F C[000w] [11 reg2 reg1] x - - - x x x x x 2 2Memory, Register 0F C[000w] [mod reg r/m] 2 2XCHG ExchangeRegister/Memory with Register 8[011w] [mod reg r/m] - - - - - - - - - 2 2 b,f f,hRegister with Accumulator 9[0 reg] 2 2XLAT Translate Byte D7 - - - - - - - - - 5 5 hXOR Boolean Exclusive ORRegister to Register 3 [00dw] [11 reg r/m] 0 - - - x x u x 0 1 1 b hRegister to Memory 3 [000w] [mod reg r/m] 1 1Memory to Register 3 [001w] [mod reg r/m] 1 1Immediate to Register/Memory 8 [00sw] [mod 110 r/m] ### 1 1Immediate to Accumulator (short form) 3 [010w] ### 1 1FlagsO D I T S Z A P CF F F F F F F F FRealModeProt’dModeClock Count(Reg/Cache Hit)RealModeProt’dModeIssueswww.national.com 226 Revision 1.3
Instruction Set (Continued)Instruction Issues for Instruction Set SummaryIssues a through c apply to real address mode only:a. This is a protected mode instruction. Attempted execution inreal mode will result in exception 6 (invalid opcode).b. Exception 13 fault (general protection) will occur in real modeif an operand reference is made that partially or fully extendsbeyond the maximum CS, DS, ES, FS, or GS segment limit(FFFFH). Exception 12 fault (stack segment limit violation ornot present) will occur in real mode if an operand reference ismade that partially or fully extends beyond the maximum SSlimit.c. This instruction may be executed in real mode. In real mode,its purpose is primarily to initialize the CPU for protectedmode.d. -Issues e through g apply to real address mode and protectedvirtual address mode:e. An exception may occur, depending on the value of the operand.f. LOCK# is automatically asserted, regardless of the presenceor absence of the LOCK prefix.g. LOCK# is asserted during descriptor table accesses.Issues h through r apply to protected virtual address modeonly:h. Exception 13 fault will occur if the memory operand in CS,DS, ES, FS, or GS cannot be used due to either a segmentlimit violation or an access rights violation. If a stack limit isviolated, an exception 12 occurs.i. For segment load operations, the CPL, RPL, and DPL mustagree with the privilege rules to avoid an exception 13 fault.The segment’s descriptor must indicate “present” or exception11 (CS, DS, ES, FS, GS not present). If the SS register isloaded and a stack segment not present is detected, anexception 12 occurs.j. All segment descriptor accesses in the GDT or LDT made bythis instruction will automatically assert LOCK# to maintaindescriptor integrity in multiprocessor systems.k. JMP, CALL, INT, RET, and IRET instructions referring toanother code segment will cause an exception 13, if an applicableprivilege rule is violated.l. An exception 13 fault occurs if CPL is greater than 0 (0 is themost privileged level).m. An exception 13 fault occurs if CPL is greater than IOPL.n. The IF bit of the Flags register is not updated if CPL is greaterthan IOPL. The IOPL and VM fields of the Flags register areupdated only if CPL = 0.o. The PE bit of the MSW (CR0) cannot be reset by this instruction.Use MOV into CR0 if desiring to reset the PE bit.p. Any violation of privilege rules as apply to the selector operanddoes not cause a Protection exception, rather, the zeroflag is cleared.q. If the processor’s memory operand violates a segment limit orsegment access rights, an exception 13 fault will occur beforethe ESC instruction is executed. An exception 12 fault willoccur if the stack limit is violated by the operand’s startingaddress.r. The destination of a JMP, CALL, INT, RET, or IRET must be inthe defined limit of a code segment or an exception 13 faultwill occur.Issue s applies to National Semiconductor-specific SMM instructions:s. All memory accesses to SMM space are non-cacheable. Aninvalid opcode exception 6 occurs unless SMI is enabled andSMAR size > 0, and CPL = 0 and [SMAC is set or if in an SMIhandler].Issue t applies to cache invalidation instruction with thecache operating in write-back mode:t. The total clock count is the clock count shown plus the numberof clocks required to write all “modified” cache lines toexternal memory.Geode GXLV Processor SeriesRevision 1.3 227 www.national.com
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Geode GXLV Processor SeriesArchitec
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Architecture Overview (Continued)Ge
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Architecture Overview (Continued)SD
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2.0 Signal DefinitionsThis section
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Signal Definitions (Continued)PinNo
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Signal Definitions (Continued)Table
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Signal Definitions (Continued)PinNo
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Page 177 and 178: Power Management (Continued)CPU Sus
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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