Geode GXLV Processor Series Low Power Integrated x86 Solutions

More documents

Recommendations

Info

Geode GXLV Processor SeriesProcessor Programming (Continued)3.3.2.1 Control RegistersA map of the Control Registers (CR0, CR1, CR2, CR3,and CR4) is shown in Table 3-6 and the bit definitions aregiven in Table 3-7. (These registers should not be confusedwith the CRRn registers.) CR0 contains system control bitswhich configure operating modes and indicate the generalstate of the CPU. The lower 16 bits of CR0 are referred toas the Machine Status Word (MSW).When operating in real mode, any program can read andwrite the control registers. In protected mode, however,only privilege level 0 (most-privileged) programs can readandwritetheseregisters.L1 Cache ControllerThe GXLV processor contains an on-board 16 KB unifieddata/instruction write-back L1 cache. With the memorycontroller on-board, the L1 cache requires no externallogic to maintain coherency. All DMA cycles automaticallysnoop the L1 cache.The CD bit (Cache Disable, bit 30) in CR0 globally controlsthe operating mode of the L1 cache. LCD and LWT,Local Cache Disable and Local Write-through bits in theTranslation Lookaside Buffer, control the mode on a pageby-pagebasis. Additionally, memory configuration controlcan specify certain memory regions as non-cacheable.If the cache is disabled, no further cache line fills occur.However, data already present in the cache continues tobe used. For the cache to be completely disabled, thecache must be invalidated with a WBINVD instructionafter the cache has been disabled.Write-back caching improves performance by relievingcongestion on slower external buses. With four dirty bits,the cache marks dirty locations on a double-word(DWORD) basis. This further reduces the number ofDWORD write operations needed during a replacement orflush operation.The GXLV processor will cache SMM regions, reducingsystem management overhead to allow for hardwareemulation such as VGA.Table 3-6. Control Registers Map31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0CR4 RegisterCR3 RegisterCR2 RegisterCR1 RegisterCR0 RegisterPGCDNWControl Register 4 (R/W)RSVDControl Register 3 (R/W)PDBR (Page Directory Base Register) RSVD 0 0 RSVDControl Register 2 (R/W)PFLA (Page Fault Linear Address)Control Register 1 (R/W)RSVDControl Register 0 (R/W)RSVDAMRSVDWPRSVDNERSVDMachine Status Word (MSW)TSTSCEMRSVDMPPETable 3-7. CR4-CR0 Bit DefinitionsBit Name DescriptionCR4 RegisterControl Register 4 (R/W)31:3 RSVD Reserved: Set to 0 (always returns 0 when read).2 TSC Time Stamp Counter Instruction:If = 1 RDTSC instruction enabled for CPL = 0 only; reset state.If = 0 RDTSC instruction enabled for all CPL states.1:0 RSVD Reserved: Set to 0 (always returns 0 when read).CR3 RegisterControl Register 3 (R/W)31:12 PDBR Page Directory Base Register: Identifies page directory base address on a 4 KB page boundary.11:0 RSVD Reserved: Set to 0.www.national.com 48 Revision 1.3
Processor Programming (Continued)Bit Name DescriptionTable 3-7. CR4-CR0 Bit Definitions (Continued)CR2 RegisterControl Register 2 (R/W)31:0 PFLA Page Fault Linear Address: With paging enabled and after a page fault, PFLA contains the linear address of theaddress that caused the page fault.CR1 RegisterControl Register 1 (R/W)31:0 RSVD ReservedCR0 RegisterControl Register 0 (R/W)31 PG Paging Enable Bit: If PG = 1 and protected mode is enabled (PE = 1), paging is enabled. After changing thestate of PG, software must execute an unconditional branch instruction (e.g., JMP, CALL) to have the changetake effect.30 CD Cache Disable: If CD = 1, no further cache line fills occur. However, data already present in the cache continuesto be used if the requested address hits in the cache. Writes continue to update the cache and cache invalidationsdue to inquiry cycles occur normally. The cache must also be invalidated with a WBINVD instruction to completelydisable any cache activity.29 NW Not Write-Through: If NW = 1, the on-chip cache operates in write-back mode. In write-back mode, writes areissued to the external bus only for a cache miss, a line replacement of a modified line, execution of a lockedinstruction, or a line eviction as the result of a flush cycle. If NW = 0, the on-chip cache operates in write-throughmode. In write-through mode, all writes (including cache hits) are issued to the external bus. This bit cannot bechanged if LOCK_NW = 1 in CCR2.28:19 RSVD Reserved18 AM Alignment Check Mask: If AM = 1, the AC bit in the EFLAGS register is unmasked and allowed to enable alignmentcheck faults. Setting AM = 0 prevents AC faults from occurring.17 RSVD Reserved16 WP Write Protect: Protects read-only pages from supervisor write access. WP = 0 allows a read-only page to bewritten from privilege level 0-2. WP = 1 forces a fault on a write to a read-only page from any privilege level.15:6 RSVD Reserved5 NE Numerics Exception: NE = 1 to allow FPU exceptions to be handled by interrupt 16. NE = 0 if FPU exceptionsare to be handled by external interrupts.4 RSVD Reserved: Do not attempt to modify, always 1.3 TS Task Switched: Set whenever a task switch operation is performed. Execution of a floating point instruction withTS = 1 causes a DNA fault. If MP = 1 and TS = 1, a WAIT instruction also causes a DNA fault.2 EM Emulate Processor Extension: If EM = 1, all floating point instructions cause a DNA fault 7.1 MP Monitor Processor Extension: If MP = 1 and TS = 1, a WAIT instruction causes Device Not Available (DNA)fault 7. The TS bit is set to 1 on task switches by the CPU. Floating point instructions are not affected by the stateof the MP bit. The MP bit should be set to one during normal operations.0 PE Protected Mode Enable: Enables the segment based protection mechanism. If PE = 1, protected mode isenabled. If PE = 0, the CPU operates in real mode and addresses are formed as in an 8086-style CPU. Refer toSection 3.9 “Protection” on page 91.Geode GXLV Processor SeriesTable 3-8. Effects of Various Combinations of EM, TS, and MP BitsCR0[3:1]Instruction TypeTS EM MP WAIT ESC0 0 0 Execute Execute0 0 1 Execute Execute1 0 0 Execute Fault 71 0 1 Fault 7 Fault 70 1 0 Execute Fault 70 1 1 Execute Fault 71 1 0 Execute Fault 71 1 1 Fault 7 Fault 7Revision 1.3 49 www.national.com
Page 4 and 5: Geode GXLV Processor SeriesTable of
Page 6 and 7: Geode GXLV Processor SeriesTable of
Page 8: Geode GXLV Processor SeriesTable of
Page 12 and 13: Geode GXLV Processor SeriesArchitec
Page 15 and 16: Architecture Overview (Continued)Ge
Page 17 and 18: Architecture Overview (Continued)SD
Page 19 and 20: 2.0 Signal DefinitionsThis section
Page 21 and 22: Signal Definitions (Continued)Index
Page 23 and 24: Signal Definitions (Continued)PinNo
Page 25 and 26: Signal Definitions (Continued)Table
Page 27 and 28: Signal Definitions (Continued)PinNo
Page 29 and 30: Signal Definitions (Continued)Table
Page 31 and 32: Signal Definitions (Continued)2.2 S
Page 33 and 34: Signal Definitions (Continued)2.2.2
Page 41 and 42: 3.0 Processor ProgrammingThis secti
Page 43 and 44: Processor Programming (Continued)3.
Page 47: Processor Programming (Continued)3.
Page 51 and 52: Processor Programming (Continued)Ta
Page 53 and 54: Processor Programming (Continued)Bi
Page 61 and 62: Processor Programming (Continued)Th
Page 65 and 66: Processor Programming (Continued)Ad
Page 69 and 70: Processor Programming (Continued)Se
Page 73 and 74: Processor Programming (Continued)TY
Page 75 and 76: Processor Programming (Continued)Ta
Page 89 and 90: Processor Programming (Continued)Wh
Page 95 and 96: Processor Programming (Continued)Bi
Page 97 and 98: Integrated Functions (Continued)4.1
Page 99 and 100:
Integrated Functions (Continued)4.1
Page 101 and 102:
Integrated Functions (Continued)Mne
Page 103 and 104:
Page 105 and 106:
Integrated Functions (Continued)Bit
Page 107 and 108:
Page 109 and 110:
Page 111 and 112:
Integrated Functions (Continued)ACT
Page 113 and 114:
Page 115 and 116:
Page 117 and 118:
Page 119 and 120:
Integrated Functions (Continued)Tab
Page 121 and 122:
Integrated Functions (Continued)SDR
Page 123 and 124:
Page 125 and 126:
Page 127 and 128:
Page 129 and 130:
Page 131 and 132:
Page 133 and 134:
Page 135 and 136:
Page 137 and 138:
Integrated Functions (Continued).Re
Page 139 and 140:
Integrated Functions (Continued)640
Page 141 and 142:
Page 143 and 144:
Integrated Functions (Continued)GX_
Page 145 and 146:
Integrated Functions (Continued)11:
Page 147 and 148:
Page 149 and 150:
Integrated Functions (Continued)9:0
Page 151 and 152:
Page 153 and 154:
Page 155 and 156:
Page 157 and 158:
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
Page 169 and 170:
Page 171 and 172:
Page 173 and 174:
Page 175 and 176:
Page 177 and 178:
Power Management (Continued)CPU Sus
Page 179 and 180:
Power Management (Continued)5.2.2 I
Page 181 and 182:
Power Management (Continued)5.3 POW
Page 183 and 184:
Power Management (Continued)Table 5
Page 185 and 186:
Electrical Specifications (Continue
Page 187 and 188:
Page 189 and 190:
Page 191 and 192:
Page 193 and 194:
Page 195 and 196:
Page 197 and 198:
Page 199 and 200:
Page 201 and 202:
Page 203 and 204:
Page 205 and 206:
Page 207 and 208:
7.0 Instruction SetThis section sum
Page 209 and 210:
Instruction Set (Continued)7.1.2.3
Page 211 and 212:
Page 213 and 214:
Page 215 and 216:
Page 217 and 218:
Instruction Set (Continued)Table 7-
Page 219 and 220:
Instruction Set (Continued)Instruct
Page 221 and 222:
Instruction Set (Continued)JMP Unco
Page 223 and 224:
Page 225 and 226:
Page 227 and 228:
Page 229 and 230:
Page 231 and 232:
Page 233 and 234:
Instruction Set (Continued)7.5 MMX
Page 235 and 236:
Instruction Set (Continued)PCMPEQB
Page 237 and 238:
Instruction Set (Continued)PUNPCKHW
Page 239 and 240:
Page 241 and 242:
Package Specifications (Continued)C
Page 243 and 244:
Package Specifications (Continued)8
Page 245 and 246:
Package Specifications (Continued)S
Page 247:
Geode GXLV Processor Series Low Pow
show all

Geode GXLV Processor Series Low Power Integrated x86 Solutions

Create successful ePaper yourself

Delete template?

Save as template?