Geode GXLV Processor Series Low Power Integrated x86 Solutions

More documents

Recommendations

Info

Geode GXLV Processor SeriesProcessor Programming (Continued)Bit Name DescriptionTable 3-17. TR5-TR3 Bit DefinitionsTR5 Register (R/W)31:12 RSVD Reserved11:4 Line Selection Line Selection:Physical address bits [11:4] used to select one of 256 lines.3:2 Set/DWORDSelectionSet/DWORD Selection:Cache read: Selects which of the four sets in the cache is used as the source for datatransferred to the cache flush buffer.Cache write: Selects which of the four sets in the cache is used as the destination for data transferredfrom the cache fill buffer.Flush buffer read: Selects which of the four DWORDs in the flush buffer is used during a TR3 read.Fill buffer write: Selects which of the four DWORDs in the fill buffer is written during a TR3 write.1:0 Control Bits Control Bits:00 = Flush read or fill buffer write.01 = Cache write.10 = Cache read.11 = Cache flush.TR4 Register (R/W)31:12 Upper TagAddressUpper Tag Address:Cache read: Upper 20 bits of tag address of the selected entry.Cache write: Data written into the upper 20 bits of the tag address of the selected entry.10 Valid Bit Valid Bit:Cache read: Valid bit for the selected entry.Cache write: Data written into the valid bit for the selected entry.9:7 LRU Bits LRU Bits:Cache read: The LRU bits for the selected line when scratchpad is disabled.xx1 = Set 0 or Set 1 most recently accessed.xx0 = Set 2 or Set 3 most recently accessed.x1x = Most recent access to Set 0 or Set 1 was to Set 0.x0x = Most recent access to Set 0 or Set 1 was to Set 1.1xx = Most recent access to Set 2 or Set 3 was to Set 2.0xx = Most recent access to Set 2 or Set 3 was to Set 3.Cache write: Ignored.6:3 Dirty Bits Dirty Bits:Cache read: The dirty bits for the selected entry (one bit per DWORD).Cache write: Data written into the dirty bits for the selected entry.2:0 RSVD Reserved: Set to 0.TR3 Register (R/W)31:0 Cache Data Cache Data:Flush buffer read: Data accessed from the cache flush buffer.Fill buffer write: Data to be written into the cache fill buffer.www.national.com 60 Revision 1.3
Processor Programming (Continued)There are five types of test operations that can be executed:• Flush buffer read• Fill buffer write• Cache write• Cache read• Cache flushThese operations are described in detail in Table 3-18. Tofill a cache line with data, the fill buffer must be written fourTable 3-18. Cache Test Operationstimes. Once the fill buffer holds a complete cache line ofdata (16 bytes), a cache write operation transfers the datafrom the fill buffer to the cache.To read the contents of a cache line, a cache read operationtransfers the data in the selected cache line to theflush buffer. Once the flush buffer is loaded, access thecontents of the flush buffer with four flush buffer readoperations.Test Operation Code Sequence Action TakenGeode GXLV Processor SeriesFlush Buffer Read MOV TR5, 0hMOV dest,TR3Set DWORD = 0, control = 00 = flush buffer read.Flush buffer (31:0) --> dest.MOV TR5, 4hMOV dest,TR3Set DWORD = 1, control = 00 = flush buffer read.Flush buffer (63:32) --> dest.MOV TR5, 8hMOV dest,TR3Set DWORD = 2, control = 00 = flush buffer read.Flush buffer (95:64) --> dest.MOV TR5, ChMOV dest,TR3Set DWORD = 3, control = 00 = flush buffer read.Flush buffer (127:96) --> dest.Fill Buffer Write MOV TR5, 0hMOV TR3, cache_dataSet DWORD = 0, control = 00 = fill buffer write.Cache_data --> fill buffer (31:0).MOV TR5, 4hMOV TR3, cache_dataSet DWORD = 1, control = 00 = fill buffer write.Cache_data --> fill buffer (63:32).MOV TR5, 8hMOV TR3, cache_dataSet DWORD = 2, control = 00 = fill buffer write.Cache_data --> fill buffer (95:64).MOV TR5, ChMOV TR3, cache_dataSet DWORD = 3, control = 00 = fill buffer write.Cache_data --> fill buffer (127:96).Cache Write MOV TR4, cache_tag Cache_tag --> tag address, valid and dirty bits.MOV TR5, line+set+control=01 Fill buffer (127:0) --> cache line (127:0).Cache ReadMOV TR5, line+set+control=10MOV dest, TR4Cache line (127:0) --> flush buffer (127:0).Cache line tag address, valid/LRU/dirty bits --> dest.Cache Flush MOV TR5, 3h Control = 11 = cache flush, all cache valid bits = 0.Revision 1.3 61 www.national.com
Page 4 and 5:
Geode GXLV Processor SeriesTable of
Page 6 and 7:
Page 8:
Page 12 and 13: Geode GXLV Processor SeriesArchitec
Page 15 and 16: Architecture Overview (Continued)Ge
Page 17 and 18: Architecture Overview (Continued)SD
Page 19 and 20: 2.0 Signal DefinitionsThis section
Page 21 and 22: Signal Definitions (Continued)Index
Page 23 and 24: Signal Definitions (Continued)PinNo
Page 25 and 26: Signal Definitions (Continued)Table
Page 27 and 28: Signal Definitions (Continued)PinNo
Page 29 and 30: Signal Definitions (Continued)Table
Page 31 and 32: Signal Definitions (Continued)2.2 S
Page 33 and 34: Signal Definitions (Continued)2.2.2
Page 41 and 42: 3.0 Processor ProgrammingThis secti
Page 43 and 44: Processor Programming (Continued)3.
Page 49 and 50: Processor Programming (Continued)Bi
Page 51 and 52: Processor Programming (Continued)Ta
Page 59: Processor Programming (Continued)3.
Page 65 and 66: Processor Programming (Continued)Ad
Page 69 and 70: Processor Programming (Continued)Se
Page 73 and 74: Processor Programming (Continued)TY
Page 75 and 76: Processor Programming (Continued)Ta
Page 89 and 90: Processor Programming (Continued)Wh
Page 97 and 98: Integrated Functions (Continued)4.1
Page 101 and 102: Integrated Functions (Continued)Mne
Page 105 and 106: Integrated Functions (Continued)Bit
Page 111 and 112:
Integrated Functions (Continued)ACT
Page 113 and 114:
Integrated Functions (Continued)Bit
Page 115 and 116:
Page 117 and 118:
Integrated Functions (Continued)4.3
Page 119 and 120:
Integrated Functions (Continued)Tab
Page 121 and 122:
Integrated Functions (Continued)SDR
Page 123 and 124:
Page 125 and 126:
Page 127 and 128:
Page 129 and 130:
Page 131 and 132:
Page 133 and 134:
Page 135 and 136:
Page 137 and 138:
Integrated Functions (Continued).Re
Page 139 and 140:
Integrated Functions (Continued)640
Page 141 and 142:
Page 143 and 144:
Integrated Functions (Continued)GX_
Page 145 and 146:
Integrated Functions (Continued)11:
Page 147 and 148:
Page 149 and 150:
Integrated Functions (Continued)9:0
Page 151 and 152:
Page 153 and 154:
Page 155 and 156:
Page 157 and 158:
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
Page 169 and 170:
Page 171 and 172:
Page 173 and 174:
Page 175 and 176:
Page 177 and 178:
Power Management (Continued)CPU Sus
Page 179 and 180:
Power Management (Continued)5.2.2 I
Page 181 and 182:
Power Management (Continued)5.3 POW
Page 183 and 184:
Power Management (Continued)Table 5
Page 185 and 186:
Electrical Specifications (Continue
Page 187 and 188:
Page 189 and 190:
Page 191 and 192:
Page 193 and 194:
Page 195 and 196:
Page 197 and 198:
Page 199 and 200:
Page 201 and 202:
Page 203 and 204:
Page 205 and 206:
Page 207 and 208:
7.0 Instruction SetThis section sum
Page 209 and 210:
Instruction Set (Continued)7.1.2.3
Page 211 and 212:
Page 213 and 214:
Page 215 and 216:
Page 217 and 218:
Instruction Set (Continued)Table 7-
Page 219 and 220:
Instruction Set (Continued)Instruct
Page 221 and 222:
Instruction Set (Continued)JMP Unco
Page 223 and 224:
Page 225 and 226:
Page 227 and 228:
Page 229 and 230:
Page 231 and 232:
Page 233 and 234:
Instruction Set (Continued)7.5 MMX
Page 235 and 236:
Instruction Set (Continued)PCMPEQB
Page 237 and 238:
Instruction Set (Continued)PUNPCKHW
Page 239 and 240:
Page 241 and 242:
Package Specifications (Continued)C
Page 243 and 244:
Package Specifications (Continued)8
Page 245 and 246:
Package Specifications (Continued)S
Page 247:
Geode GXLV Processor Series Low Pow
show all

Geode GXLV Processor Series Low Power Integrated x86 Solutions

Create successful ePaper yourself

Delete template?

Save as template?