Geode GXLV Processor Series Low Power Integrated x86 Solutions

Geode GXLV Processor SeriesIntegrated Functions (Continued)4.3.4 Memory Controller Register DescriptionThe Memory Controller maps 100h locations starting atGX_BASE+8400h. Refer to Section 4.1.2 “Control Registers”on page 99 for instructions on accessing these registers.Table 4-14. Memory Controller Register SummaryTable 4-14 summarizes the 32-bit registers contained inthe memory controller. Table 4-15 gives detailed register/bitformats.GX_BASE+Memory Offset Type Name/Function Default Value8400h-8403h R/W MC_MEM_CNTRL1Memory Controller Control Register 1: Memory controller configuration information(e.g., refresh interval, SDCLK ratio, etc.). BIOS must program this registerbased on the processor frequency and desired SDCLK divide ratio.248C0040h8404h-8407h R/W MC_MEM_CNTRL2Memory Controller Control Register 2: Memory controller configuration informationto control SDCLK. BIOS must program this register based on the processorfrequency and the SDCLK divide ratio.8408h-840Bh R/W MC_BANK_CFGMemory Controller Bank Configuration: Contains the configuration information forthe each of the four SDRAM banks in the memory array. BIOS must program thisregister during boot by running an autosizing routine on the memory.840Ch-840Fh R/W MC_SYNC_TIM1Memory Controller Synchronous Timing Register 1: SDRAM memory timinginformation - This register controls the memory timing of all four banks of DRAM.BIOS must program this register based on the processor frequency and theSDCLK divide ratio.8414h-8417h R/W MC_GBASE_ADDMemory Controller Graphics Base Address Register: This register sets thegraphics memory base address, which is programmable on 512 KB boundaries.The display controller and the graphics pipeline generate a 20-bit DWORD offsetthat is added to the graphics memory base address to form the physical memoryaddress. Typically, the graphics memory region is located at the top of physicalmemory.8418h-841Bh R/W MC_DR_ADDMemory Controller Dirty RAM Address Register: This register is used to set theDirty RAM address index for processor diagnostic access. This register should beinitialized before accessing the MC_DR_ACC register841Ch-841Fh R/W MC_DR_ACCMemory Controller Dirty RAM Access Register: This register is used to accessthe Dirty RAM. A read/write to this register will access the Dirty RAM at theaddress specified in the MC_DR_ADD register.00000801h41104110h2A733225h00000000h00000000h0000000xhwww.national.com 112 Revision 1.3