Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesElectrical Specifications (Continued)Table 6-17. SDRAM Interface Signals (Refer to Figures 6-9 and 6-10)Symbol Parameter Min Max Unitt1RASA#, RASB#, CASA#, CASB#,WEA#, WEB#, CKEA, CKEB,DQM[7:0], CS[3:0]# Ouput Valid fromSDCLK[3:0]t1Min=z–1.5 t1Max=z–1.0 nst2 MA[12:0], BA[1:0] Output Valid from t2Min=z–1.7 t2Max=z–1.2 nsSDCLK[3:0]t3 MD[63:0] Output Valid fromt2Min=z–1.6 t3Max=z–0.3 nsSDCLK[3:0]t4 MD[63:0] Read Data in Setup to0 nsSDCLK_INt5 MD[63:0] Read Data Hold to2.0 nsSDCLK_INCalculation of minimum and maximum values of t1, t2, and t3: (seeFigure4-10onpage124)x =shift value applied to SHFTSDCLK field where SHFTSDCLK field = GX_BASE+8404h[5:3].y=coreclockperiod÷2z=(x*y)Equation Example:A 200 MHz GXLV processor interfacing with a 66 MHz SDRAM bus, having a shift value of 2:x=2core clock period = 1/(200 MHz) = 5 nsy=5÷2t1Min=(2*(5÷2))–1.5=3.5nst1 Max = (2 * (5 ÷ 2)) – 1.0 = 4.0 nst1, t2, t3SDCLK[3:0]CNTRL, MA[12:0],BA[1:0], MD[63:0]ValidFigure 6-9. Output Valid Timingt4t5SDCLK_INMD[63:0]Read Data InData ValidData ValidFigure 6-10. Setup and Hold Timings - Read Data Inwww.national.com 202 Revision 1.3
Electrical Specifications (Continued)Table 6-18. Video Interface Signals (Refer to Figures 6-11 through 6-13)Symbol Parameter Min Max Unitt1 PCLK Period 6.5 40 nst2 PCLK High Time 3 nst3 PCLK Low Time 3 nst4PIXEL[17:0], CRT_HSYNC, CRT_VSYNC, FP_HSYNC,2 5 nsFP_VSYNC, ENA_DISP Valid Delay from PCLK Rising Edget5 VID_CLK Period 8.5 nst6 VID_RDY Setup to VID_CLK Rising Edge 5 nst7 VID_RDY Hold to VID_CLK Rising Edge 2 nst8 VID_VAL, VID_DATA[7:0] Valid Delay from VID_CLK Rising Edge 2 5 nst9 DCLK Period 6.5 nst10 DCLK Rise/Fall Time 2 nstcyc DCLK Duty Cycle 40 60 %Geode GXLV Processor Seriest1t4t2t3PCLKPIXEL[17:0],CRT_HSYNC, CRT_VSYNC,FP_HSYNC, FP_VSYNC,ENA_DISPData ValidData ValidFigure 6-11. Graphics Port TimingRevision 1.3 203 www.national.com
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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