Geode GXLV Processor Series Low Power Integrated x86 Solutions

Processor Programming (Continued)3.3.2.4 TLB Test RegistersTwo test registers are used in testing the processor’sTranslation Lookaside Buffer (TLB), TR6 and TR7. Table 3-14 is a register map for the TLB Test Registers with their bitdefinitions given in Table 3-15 on page 58. The test registersare accessed through MOV instructions that can beexecuted only at privilege level 0 (real mode is alwaysprivilege level 0).The CPU TLB is a 32-entry, four-way set associativememory. Each TLB entry consists of a 24-bit tag and 20-bit data. The 24-bit tag represents the high-order 20 bitsof the linear address, a valid bit, and three attribute bits.The 20-bit data portion represents the upper 20 bits of thephysical address that corresponds to the linear address.The TLB Test Control Register (TR6) contains a commandbit, the upper 20 bits of a linear address, a valid bitand the attribute bits used in the test operation. The contentsof TR6 are used to create the 24-bit TLB tag duringboth write and read (TLB lookup) test operations. Thecommand bit defines whether the test operation is a reador a write.The TLB Test Data Register (TR7) contains the upper 20bits of the physical address (TLB data field), three LRUbits, two replacement (REP) bits, and a control bit (PL).During TLB write operations, the physical address in TR7is written into the TLB entry selected by the contents ofTR6. During TLB lookup operations, the TLB dataselected by the contents of TR6 is loaded into TR7. Table3-15 lists the bit definitions for TR7 and TR6.Geode GXLV Processor SeriesTable 3-14. TLB Test Registers31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0TR7 RegisterTR6 RegisterTLB Test Data Register (R/W)Physical Address 0 0 TLB LRU 0 0 PLTLB Test Control Register (R/W)Linear Address V D D#UU#RR#REP 0 00 0 0 0 CRevision 1.3 57 www.national.com