Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesProcessor Programming (Continued)Bit Name DescriptionTable 3-11. Configuration RegistersIndex C1h CCR1 — Configuration Control Register 1 (R/W) Default Value = 00h7:3 RSVD Reserved: Set to 0.2:1 SMAC System Management Memory Access:If = 00: SMM is disabled.If = 01: SMI# pin is active to enter SMM. SMINT instruction is inactive.If = 10: SMM is disabled.If = 11: SMINT instruction is active to enter SMM. SMI# pin is inactive.Note: SMI_LOCK (CCR3[0]) must = 0, or the CPU must be in SMI mode, to write this bit.0 RSVD Reserved: Set to 0.Note: Bits 1 and 2 are cleared to zero at reset.Index C2h CCR2 — Configuration Control Register 2 (R/W) Default Value = 00h7 USE_SUSP Enable Suspend Pins:If = 1: SUSP# input and SUSPA# output are enabled.If = 0: SUSP# input is ignored.6 RSVD Reserved: This is a test bit that must be set to 0.5 RSVD Reserved: Set to 0.4 WT1 Write-Through Region 1:If = 1: Forces all writes to the address region between 640 KB to 1 MB that hit in the on-chip cache tobe issued on the external bus.3 SUSP_HLT Suspend on HALT:If = 1: CPU enters Suspend mode following execution of a HALT instruction.2 LOCK_NW Lock NW Bit:If = 1: Prohibits changing the state of the NW bit (CR0[29]) (refer to Table 3-7 on page 49).Set to 1 after setting NW.1:0 RSVD Reserved: Set to 0.Note: All bits are cleared to zero at reset.Index C3h CCR3 — Configuration Control Register 3 (R/W) Default Value = 00h7 LSS_34 Load/Store Serialize 3 GB to 4 GB:If = 1: Strong R/W ordering imposed in address range C0000000h to FFFFFFFFh.6 LSS_23 Load/Store Serialize 2 GB to 3 GB:If = 1: Strong R/W ordering imposed in address range 80000000h to BFFFFFFFh.5 LSS_12 Load/Store Serialize 1 GB to 2 GB:If = 1: Strong R/W ordering imposed in address range 40000000h to 7FFFFFFFh.4 MAPEN Map Enable:If = 1: All configuration registers are accessible. All accesses to I/O Port 22h are trapped.If = 0: Only configuration registers Index C1h-C3h, CDh-CFh FEh, FFh (CCRn, SMAR, DIRn) areaccessible. Other configuration registers (including PCR, SMHRn, GCR, VGACTL, VGAM0) are notaccessible.3 SUSP_SMM_EN Enable Suspend in SMM Mode:If 0 = SUSP# ignored in SMM mode.If 1 = SUSP# recognized in SMM mode.2 RSVD Reserved: Set to 0.1 NMI_EN NMI Enable:If = 1: NMI is enabled during SMM.If = 0: NMI is not recognized during SMM.Note: SMI_LOCK (CCR3[0]) must = 0 or the CPU must be in SMI mode to write to this bit.0 SMI_LOCK SMM Register Lock:If = 1: SMM Address Region Register (SMAR[31:0]), SMAC (CCR1[2]), USE_SMI (CCR1[1])cannot be modified unless in SMM routine. Once set, SMI_LOCK can only be cleared by assertingthe RESET pin.Note: All bits are cleared to zero at reset.www.national.com 52 Revision 1.3
Processor Programming (Continued)Bit Name DescriptionTable 3-11. Configuration Registers (Continued)Index E8h CCR4 — Configuration Control Register 4 (R/W) Default Value = 85h7 CPUID Enable CPUID Instruction:If = 1: The ID bit in the EFLAGS register to be modified and execution of the CPUID instruction occursas documented in Section 7.2 “CPUID Instruction” on page 212.If = 0: The ID bit can not be modified and execution of the CPUID instruction causes an invalid opcodeexception.6 SMI_NEST SMI Nest:If = 1: SMI interrupts can occur during SMM mode. SMM service routines can optionally setSMI_NEST high to allow higher-priority SMI interrupts while handling the current event5 FPU_FAST_EN FPU Fast Mode Enable:If = 0: Disable FPU Fast ModeIf = 1: Enable FPU Fast Mode.4 DTE_EN Directory Table Entry Cache:If = 1: Enables directory table entry to be cached.Clearedto0atreset.3 MEM_BYP Memory Read Bypassing:If = 1: Enables memory read bypassing.Clearedto0atreset.2:0 IORT(2:0) I/O Recovery Time: Specifies the minimum number of bus clocks between I/O accesses:000 = No clock delay 100 = 16-clock delay001 = 2-clock delay 101 = 32-clock delay (default value after reset)010 = 4-clock delay 110 = 64-clock delay011 = 8-clock delay 111 = 128-clock delayNote: MAPEN (CCR3[4]) must = 1 to read or write this register.Geode GXLV Processor SeriesIndex EBh CCR7 — Configuration Control Register 7 (R/W) Default Value = 00h7:3 RSVD Reserved: Set to 0.2 NMI Generate NMI:If 0 = Do nothingIf 1 = Generate NMIIn order to generate multiple NMIs, this bit must be set to zero between each setting of 1.1 RSVD Reserved: Set to 0.0 EMMX Extended MMX Instructions Enable:If = 1: Extended MMX instructions are enabledIndex 20h PCR — Performance Control Register (R/W) Default Value = 07h7 LSSER Load/Store Serialize Enable (Reorder Disable): LSSER should be set to ensure that memorymapped I/O devices operating outside of the address range 640 KB to 1 MB will operate correctly. Formemory accesses above 1 GByte, refer to CCR3[7:5] (LSS_34, LSS_23, LSS_12.)If = 1: All memory read and write operations will occur in execution order (load/store serializingenabled, reordering disabled).If = 0: Memory reads and write can be reordered for optimum performance (load/store serializing disabled,reordering enabled).Memory accesses in the address range 640 KB to 1 MB will always be issued in execution order.6 RSVD Reserved: Set to 0.5 RSVD Reserved: Set to 1.4:0 RSVD Reserved: Set to 0.Note: MAPEN (CCR3[4]) must = 1 to read or write this register.Revision 1.3 53 www.national.com
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Geode GXLV Processor Series Low Pow
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