Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesElectrical Specifications (Continued)Symbolt12t13Notes: 1.ParameterTable 6-14. Clock Signals (Refer to Figures 6-5 and 6-6) (Continued)SYSCLK = 33 MHzSDCLK_OUT, SDCLK[3:0] Fall Time166 MHz / 2.5 0.5 ns Note 3180 MHz / 2.5 0.5180 MHz / 3 0.5200 MHz / 3 0.5233 MHz / 3 0.5233 MHz / 3.5 0.5266 MHz / 3.5 0.5266 MHz / 4 0.5SDCLK_OUT, SDCLK[3:0] Rise Time166 MHz 0.45 ns Note 3180 MHz 0.45180 MHz200 MHz 0.45233 MHz 0.45233 MHz266 MHz 0.45266 MHzA SYSCLK of 30 MHz corresponds to a core frequency of 180 MHz. A SYSCLK of 33 MHz corresponds tocore frequencies of 166, 200, 233, and 266 MHz.2. SDCLK calculations are based on the following officially supported configurations:166 MHz (5x) / 2.5 = 66.4 MHz SDCLK_OUT180 MHz (5x) / 2.5 = 72 MHz SDCLK_OUT180 MHz (6x) / 3 = 60 MHz SDCLK_OUT200 MHz (6x) / 3 = 66.7 MHz SDCLK_OUT233 MHz (7x) / 3 = 77.7 MHz SDCLK_OUT233 MHz (7x) / 3.5 = 66.6 MHz SDCLK_OUT266 MHz (8x) / 3.5 = 76 MHz SDCLK_OUT266 MHz (8x) / 4 = 66.5 MHz SDCLK_OUTSYSCLK = 30 MHzMin Typ Max Min Typ MaxUnitsComments3. SDCLK_OUT and SYSCLK rise and fall times are measured between V IH min and V IL max with a 50 pFload.www.national.com 198 Revision 1.3
Electrical Specifications (Continued)t1t3V IH(Min)1.5VV IL(Max)SYSCLKt6t4t5Geode GXLV Processor SeriesFigure 6-5. SYSCLK Timing and Measurement Pointst9t10V IH (Min)1.5VV IL (Max)SDCLK_OUT,SDCLK[3:0]t13t11t12Figure 6-6. SDCLK[3:0] Timing and Measurement PointsRevision 1.3 199 www.national.com
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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