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Geode GXLV Processor SeriesProcessor Programming (Continued)3.7.8.2 CPU States Related to SMM and SuspendModeThe state diagram shown in Figure 3-12 illustrates the variousCPU states associated with SMM and Suspendmode. While in the SMM service routine, the GXLV processorcore can enter Suspend mode either by (1) executinga halt (HLT) instruction or (2) by asserting the SUSP#input.During SMM operations and while in SUSP#-initiatedSuspend mode, an occurrence of either NMI or INTR isSuspend Mode(SUSPA# = 0)NMI or INTRlatched. (In order for INTR to be latched, the IF flag,EFLAGS register bit 9, must be set.) The INTR or NMI isserviced after exiting Suspend mode.If Suspend mode is entered through a HLT instructionfrom the operating system or application software, thereception of an SMI# interrupt causes the CPU to exitSuspend mode and enter SMM. If Suspend mode isentered through the hardware (SUSP# = 0) while theoperating system or application software is active, theCPU latches one occurrence of INTR, NMI, and SMI#.Interrupt ServiceRoutineHLT*IRET*NMI or INTRRESETOS/ApplicationSoftwareSUSP# = 0SUSP# = 1Suspend Mode(SUSPA# = 0)SMI# = 0SMI# = 0SMINT*RSM*(INTR, NMI and SMI# latched)Non-SMM OperationsSMM OperationsSMM Service Routine(SMI# = 0)HLT*NMI or INTRIRET*IRET*Suspend Mode(SUSPA# = 0)*InstructionsInterrupt ServiceRoutineSUSP# = 0 SUSP# = 1Suspend Mode(SUSPA# = 0)(INTR and NMI latched)Interrupt ServiceRoutineNMI or INTRFigure 3-12. SMM and Suspend Mode State Diagramwww.national.com 90 Revision 1.3
Processor Programming (Continued)3.8 HALT AND SHUTDOWNThe halt instruction (HLT) stops program execution andgenerates the Halt bus cycle on the PCI bus. The GXLVprocessor core then drives out a Stop Grant bus cycle andenters a low-power Suspend mode if the SUSP_HLT bit inCCR2 (Index C2h[3]) is set. SMI#, NMI, INTR with interruptsenabled (IF bit in EFLAGS = 1), or RESET forcesthe CPU out of the halt state. If the halt state is interrupted,the saved code segment and instruction pointerspecify the instruction following the HLT.Shutdown occurs when a severe error is detected thatprevents further processing. The most common severeerror is the triple fault, a fault event while handling a doublefault. Setting the IDT limit to zero or the GDT limit tozero will cause a triple fault when in protected mode.A RESET brings the processor out of shutdown. An NMIwill work if the IDT limit is large enough, at least 000Fh, tocontain the NMI interrupt vector and if the stack hasenough room. The stack must be large enough to containthe vector and flag information (the stack pointer must begreater than 0005h).3.9 PROTECTIONSegment protection and page protection are safeguardsbuilt into the GXLV processor’s protected-mode architecturethat deny unauthorized or incorrect access toselected memory addresses. These safeguards allowmultitasking programs to be isolated from each other andfrom the operating system. This section concentrates onsegment protection.Selectors and descriptors are the key elements in the segmentprotection mechanism. The segment base address,size, and privilege level are established by a segmentdescriptor. Privilege levels control the use of privilegedinstructions, I/O instructions and access to segments andsegment descriptors. Selectors are used to locate segmentdescriptors.Segment accesses are divided into two basic types, thoseinvolving code segments (e.g., control transfers) andthose involving data accesses. The ability of a task toaccess a segment depends on the:• Segment type• Instruction requesting access• Type of descriptor used to define the segment• Associated privilege levels (described next)Data stored in a segment can be accessed only by codeexecuting at the same or a more privileged level. A codesegment or procedure can only be called by a task executingat the same or a less privileged level.3.9.1 Privilege LevelsThe values for privilege levels range between 0 and 3.Level 0 is the highest privilege level (most privileged), andlevel 3 is the lowest privilege level (least privileged). Theprivilege level in real mode is zero.The Descriptor Privilege Level (DPL) is the privilegelevel defined for a segment in the segment descriptor. TheDPL field specifies the minimum privilege level needed toaccess the memory segment pointed to by the descriptor.The Current Privilege Level (CPL) is defined as the currenttask’s privilege level. The CPL of an executing task isstored in the hidden portion of the code segment registerand essentially is the DPL for the current code segment.The Requested Privilege Level (RPL) specifies a selector’sprivilege level. RPL is used to distinguish betweenthe privilege level of a routine actually accessing memory(the CPL), and the privilege level of the original requester(the RPL) of the memory access. The lesser of the RPLand CPL is called the Effective Privilege Level (EPL). Therefore,if RPL = 0 in a segment selector, the EPL is alwaysdetermined by the CPL. If RPL = 3, the EPL is always 3regardless of the CPL. If the level requested by RPL isless than the CPL, the RPL level is accepted and the EPLis changed to the RPL value. If the level requested by RPLis greater than CPL, the CPL overrides the requested RPLand EPL becomes the CPL value.For a memory access to succeed, the EPL must be atleast as privileged as the Descriptor Privilege Level (EPL≤ DPL). If the EPL is less privileged than the DPL (EPL >DPL), a general protection fault is generated. For example,if a segment has a DPL = 2, an instruction accessingthe segment only succeeds if executed with an EPL ≤ 2.3.9.2 I/O Privilege LevelsThe I/O Privilege Level (IOPL) allows the operating systemexecuting at CPL = 0 to define the least privilegedlevel at which IOPL-sensitive instructions can unconditionallybe used. The IOPL-sensitive instructions include CLI,IN, OUT, INS, OUTS, REP INS, REP OUTS, and STI.Modification of the IF bit in the EFLAGS register is alsosensitive to the I/O privilege level.TheIOPLisstoredintheEFLAGSregister(bits[31:12]).An I/O permission bit map is available as defined by the32-bit Task State Segment (TSS). Since each task canhave its own TSS, access to individual I/O ports can begranted through separate I/O permission bit maps.If CPL ≤ IOPL, IOPL-sensitive operations can be performed.If CPL > IOPL, a general protection fault is generatedif the current task is associated with a 16-bit TSS. Ifthe current task is associated with a 32-bit TSS and CPL> IOPL, the CPU consults the I/O permission bitmap in theTSS to determine on a port-by-port basis whether or not I/Oinstructions (IN, OUT, INS, OUTS, REP INS, REP OUTS)are permitted. The remaining IOPL-sensitive operationsgenerate a general protection fault.Geode GXLV Processor SeriesRevision 1.3 91 www.national.com
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Geode GXLV Processor Series Low Pow
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