Geode GXLV Processor Series Low Power Integrated x86 Solutions

Signal Definitions (Continued)2.2.3 Memory Controller Interface Signals (Continued)Signal NameDQM[7:0]SDCLK[3:0]BGAPin No.RefertoTable 2-3AE4,AF5,AE5,AF4SPGAPin No. Type DescriptionRefertoTable 2-5AM8,AK10,AL7,AK8OOData Mask Control BitsDuring memory read cycles, these outputs control whether theSDRAM output buffers are driven on the MD bus or not. All DQMsignals are asserted during read cycles.During memory write cycles, these outputs control whether ornotMDdatawillbewrittenintotheSDRAM.DQM[0] is associated with MD[7:0].DQM[7] is associated with MD[63:56].SDRAM ClocksThe SDRAM devices sample all the control, address, and databased on these clocks.SDCLK_IN AE8 AK12 I SDRAM Clock InputThe GXLV processor samples the memory read data on thisclock. Works in conjunction with the SDCLK_OUT signal.SDCLK_OUT AF8 AL13 O SDRAM Clock OutputThis output is routed back to SDCLK_IN. The board designershould vary the length of the board trace to control skewbetween SDCLK_IN and SDCLK.Geode GXLV Processor Series2.2.4 Video Interface SignalsSignal NameBGAPin NoSPGAPin No Type DescriptionPCLK AC1 AJ1 O Pixel Port ClockPCLK is the pixel dot clock output. It clocks the pixel data fromthe GXLV processor to the CS5530.VID_CLK P1 V4 O Video ClockVID_CLK is the video port clock to the CS5530.DCLK AB1 AD4 I Dot ClockThe DCLK input is driven from the CS5530 and is the pixel dotclock. In some cases this clock can be a 2x multiple of PCLKCRT_HSYNC W2 AD2 O CRT Horizontal SyncCRT Horizontal Sync establishes the line rate and horizontalretrace interval for an attached CRT. The polarity is programmable.See DC-Timing_CFG Register in Table 4-29 on page 146 forprogramming information.CRT_VSYNC AA3 AH2 O CRT Vertical SyncCRT Vertical Sync establishes the screen refresh rate and verticalretrace interval for an attached CRT. The polarity is programmable.See DC-Timing_CFG Register in Table 4-29 on page 147for programming information.Revision 1.3 37 www.national.com