Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesIntegrated Functions (Continued)4.5.8.1 Configuration and Status RegistersThe Configuration and Status Registers group consists offour 32-bit registers located at GX_BASE+8300h-830Ch.Bit Name DescriptionThese registers are described below and Table 4-29 givestheir bit formats.Table 4-29. Display Controller Configuration and Status RegistersGX_BASE+8300h-8303h DC_UNLOCK Register (R/W) Default Value = 00000000h31:16 RSVD Reserved: Set to 0.15:0 UNLOCK_CODEUnlock Code: This register must be written with the value 4758h in order to write to the protected registers.The following registers are protected by the locking mechanism. Writing any other value enables thewrite lock function.DC_GENERAL_CFG DC_LINE_DELTA DC_V_TIMING_2DC_TIMING_CFG DC_BUF_SIZE DC_V_TIMING_3DC_OUTPUT_CFG DC_H_TIMING_1 DC_FP_V_TIMINGDC_FB_ST_OFFSET DC_H_TIMNG_2DC_CB_ST_OFFSET DC_H_TIMING_3DC_CUR_ST_OFFSET DC_FP_H_TIMINGDC_VID_ST_OFFSET DC_V_TIMING_1GX_BASE+8304h-8307h DC_GENERAL_CFG (R/W) (Locked) Default Value = 00000000h31 DDCK Divide Dot Clock: Divide internal DCLK by two relative to PCLK:0 = Disable; 1 = Enable.30 DPCK Divide Pixel Clock: Divide PCLK by two relative to internal DCLK:0 = Disable; 1 = Enable.29 VRDY Video Ready Protocol: 0 = Low speed video port: 1 = High speed video port.Always program to 1.28 VIDE Video Enable: Motion video port: 0 = Disable; 1 = Enable.27 SSLC Split-screen Line Compare: VGA line compare function: 0 = Disable; 1 = Enable.When enabled, the internal line counter will be compared to the value programmed in the DC_SS_LINE_CMP register. If it matches, the frame buffer address will be reset to zero. This enables a splitscreen function.26 CH4S Chain 4 Skip: Allow display controller to read every 4th DWORD from the frame buffer for compatibilitywith the VGA: 0 = Disable; 1 = Enable.25 DIAG FIFO Diagnostic Mode: This bit allows testability of the on-chip Display FIFO and Compressed LineBuffer via the diagnostic access registers. A low-to-high transition will reset the Display FIFO’s R/W pointersand the Compressed Line Buffer’s read pointer. 0 = Normal operation; 1 = Enable.24 LDBL Line Double: Allow line doubling for emulated VGA modes: 0 = Disable; 1 = Enable.If enabled, this will cause each odd line to be replicated from the previous line as the data is sent to the display.Timing parameters should be programmed as if pixel doubling is not used, however, the frame buffershould be loaded with half the normal number of lines.23:19 RSVD Reserved: Set to 0.18 FDTY Frame Dirty Mode: Allow entire frame to be flagged as dirty whenever a pixel write occurs to the framebuffer (this is provided for modes that use a linearly mapped frame buffer for which the line delta is notequal to 1024 or 2048 bytes): 0 = Disable; 1 = Enable.When disabled, dirty bits are set according to the Y address of the pixel write.17 RSVD Reserved: Set to 0.16 CMPI Compressor Insert Mode: Insert one static frame between update frames: 0 = Disable; 1 = Enable.An update frame is a frame in which dirty lines are updated. Conversely, a static frame is a frame in whichdirty lines are not updated (the display image may not actually be static, because lines that are not compressedsuccessfully must be retrieved from the uncompressed frame buffer).15:12 DFIFOHI-PRI ENDLVLDisplay FIFO High Priority End Level: This field specifies the depth of the display FIFO (in 64-bit entriesx 4) at which a high-priority request previously issued to the memory controller will end. The value isdependent upon display mode.This register should always be non-zero and should be larger than the start level.www.national.com 144 Revision 1.3
Integrated Functions (Continued)11:8 DFIFOHI-PRISTART LVL7:6 DCLK_MULTable 4-29. Display Controller Configuration and Status Registers (Continued)Bit Name DescriptionDisplay FIFO High Priority Start Level: This field specifies the depth of the display FIFO (in 64-bit entriesx 4) at which a high-priority request will be sent to the memory controller to fill up the FIFO. The value isdependent upon display mode.This register should always be nonzero and should be less than the high-priority end level.DCLK Multiplier: This 2-bit field specifies the clock multiplier for the input DCLK pin. After the input clockis optionally multiplied, the internal DCLK and PCLK may be divided as necessary.00 = Forced Low01 = DCLK ÷ 210 = DCLK11 = 2 x DCLK5 DECE Decompression Enable: Allow operation of internal decompression hardware:0 = Disable; 1 = Enable.4 CMPE Compression Enable: Allow operation of internal compression hardware: 0 = Disable; 1 = Enable3 PPC Pixel Panning Compatibility: This bit has the same function as that found in the VGA.Allow pixel alignment to change when crossing a split-screen boundary - it will force the pixel alignment tobe 16-byte aligned: 0 = Disable; 1 = Enable.If disabled, the previous alignment will be preserved when crossing a split-screen boundary.2 DVCK Divide Video Clock: Selects frequency of VID_CLK pin:0 = VID_CLK pin frequency is equal to one-half (½) the frequency of the core clock.1 = VID_CLK pin frequency is equal to one-fourth (¼) the frequency of the core clock.Note: Bit 28 (VIDE) must be set to 1 for this bit to be valid.1 CURE Cursor Enable: Use internal hardware cursor: 0 = Disable; 1 = Enable.0 DFLE Display FIFO Load Enable: Allow the display FIFO to be loaded from memory:0 = Disable; 1 = Enable.If disabled, no write or read operations will occur to the display FIFO.If enabled, a flat panel should be powered down prior to setting this bit low. Similarly, if active, a CRTshould be blanked prior to setting this bit low.Geode GXLV Processor SeriesGX_BASE+8308h-830Bh DC_TIMING_CFG Register (R/W) (Locked) Default Value = xxx00000h31 VINT(RO)30 VNA(RO)29 DNA(RO)28 RSVD Reserved: Set to 0.27 DDCI(RO)Vertical Interrupt (Read Only): Is a vertical interrupt pending? 0 = No; 1 = Yes.This bit is provided to maintain backward compatibility with the VGA. It corresponds to VGA port 3C2h bit7.Vertical Not Active (Read Only): Is the active part of a vertical scan is in progress (i.e., retrace, blanking,or border)? 0 = Yes; 1 = No.This bit is provided to maintain backward compatibility with the VGA. It corresponds to VGA port 3BA/3DAbit 3.Display Not Active (Read Only): Is the active part of a line is being displayed (i.e., retrace, blanking, orborder)? 0 = Yes; 1 = No.This bit is provided to maintain backward compatibility with the VGA. It corresponds to VGA port 3BA/3DAbit 0.DDC Input (Read Only): This bit returns the value from the DDCIN pin that should reflect the value frompin 12 of the VGA connector. It is used to provide support for the VESA Display Data Channel standardlevel DDC1.26:20 RSVD Reserved: Set to 0.19:17 RSVD Reserved: Set to 0.16 BKRT Blink Rate:0 = Cursor blinks on every 16 frames for a duration of 8 frames (approximately 4 times per second) andVGA text characters will blink on every 32 frames for a duration of 16 frames (approximately 2 times persecond).1 = Cursor blinks on every 32 frames for a duration of 16 frames (approximately 2 times per second) andVGA text characters blink on every 64 frames for a duration of 32 frames (approximately 1 time per second).Blinking is enabled by BLNK bit 7.Revision 1.3 145 www.national.com
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Geode GXLV Processor Series Low Pow
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