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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Electrical Specifications (Continued)6.2 ELECTRICAL CONNECTIONS6.2.1 <strong>Power</strong>/Ground Connections and DecouplingTesting and operating the <strong>GXLV</strong> processor requires theuse of standard high frequency techniques to reduce parasiticeffects. These effects can be minimized by filteringthe DC power leads with low-inductance decouplingcapacitors, using low-impedance wiring, and by connectingall V CC2 and V CC3 pins to the appropriate voltage levels.6.2.1.1 <strong>Power</strong> PlanesFigure 6-1 shows layout recommendations for splitting thepower plane between V CC2 (core: 2.2V, 2.5V, 2.9V) andV CC3 (I/O: 3.3V) volts in the BGA package. The illustrationassumes there is one power plane, and no componentson the back of the board.Figure 6-2 shows layout recommendations for splitting thepower plane between V CC2 (core: 2.2V, 2.5V, 2.9V) andV CC3 (I/O: 3.3V) volts in the SPGA package.<strong>Geode</strong> <strong>GXLV</strong> <strong>Processor</strong> <strong>Series</strong>3.3V Plane(V CC3 )A1 26A2.2V, 2.5V, or 2.9V Plane(V CC2 )3.3V Plane(V CC3 )<strong>Geode</strong> <strong>GXLV</strong><strong>Processor</strong>352 BGA - Top View3.3V Plane(V CC3 )2.2V, 2.5V, or 2.9V Plane(V CC2 )AF126AFLegend= High frequency capacitor= 220 µF, low ESR capacitor= 3.3V connection= 2.2V, 2.5V, or 2.9V connection3.3V Plane(V CC3 )Note: Where signals cross plane splits, it is recommended to includeAC decoupling between planes with 47 pF capacitors.Figure 6-1. BGA Recommended Split <strong>Power</strong> Plane and DecouplingRevision 1.3 185 www.national.com

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