Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesSignal Definitions (Continued)2.2.1 System Interface Signals (Continued)Signal NameBGAPin No.SPGAPin No. Type DescriptionSMI# C19 B28 I System Management InterruptSMI# is a level-sensitive interrupt. SMI# puts the GXLV processorinto System Management Mode (SMM).SUSP#H2(PU)M4(PU)I Suspend RequestThis signal is used to request that the GXLV processor enterSuspend mode. After recognition of an active SUSP# input, theprocessor completes execution of the current instruction, anypending decoded instructions and associated bus cycles.SUSP# is enabled by setting the SUSP bit in CCR2, and isignored following RESET. (See Table 3-11 on page 52 for CCR2bit definitions.)Since the GXLV processor includes system logic functions aswell as the CPU core, there are special modes designed to supportthe different power management states associated withAPM, ACPI, and portable designs. The part can be configured tostop only the CPU core clocks, or all clocks. When all clocks arestopped, the external clock can also be stopped. (See Section5.0 “Power Management” on page 176 for more details regardingpower management states.)This pin is internally connected to a weak (>20-kohm) pull-upresistor.SUSPA# E2 H4 O Suspend AcknowledgeSuspend Acknowledge indicates that the GXLV processor hasentered low-power Suspend mode as a result of SUSP# assertionor execution of a HALT instruction. SUSPA# floats followingRESET and is enabled by setting the SUSP bit in CCR2. (SeeTable 3-11 on page 52 for CCR2 bit definitions.)The SYSCLK input may be stopped after SUSPA# has beenasserted to further reduce power consumption if the system isconfigured for 3V Suspend mode. (see Section 5.1.4 “3 Volt Suspend”on page 177 for details regarding this mode).SERIALP L3 Q1 O Serial PacketSerial Packet is the single wire serial-transmission signal to theCS5530 chip. The clock used for this interface is SYSCLK. Thisinterface carries packets of miscellaneous information to thechipset to be used by the VSA technology software handlers.www.national.com 32 Revision 1.3
Signal Definitions (Continued)2.2.2 PCI Interface SignalsSignal NameFRAME#IRDY#TRDY#STOP#BGAPin No.A8(PU)C9(PU)B9(PU)C11(PU)SPGAPin No Type DescriptionC13(PU)D14(PU)B14(PU)A15(PU)s/t/ss/t/ss/t/ss/t/sFrameFRAME# is driven by the current master to indicate the beginningand duration of an access. FRAME# is asserted to indicatea bus transaction is beginning. While FRAME# is asserted, datatransfers continue. When FRAME# is deasserted, the transactionis in the final data phase.This pin is internally connected to a weak (>20-kohm) pull-upresistor.Initiator ReadyIRDY#isassertedtoindicatethatthebusmasterisabletocompletethe current data phase of the transaction. IRDY# is used inconjunctionwithTRDY#.AdataphaseiscompletedonanySYSCLK in which both IRDY# and TRDY# are sampledasserted. During a write, IRDY# indicates valid data is presenton AD[31:0]. During a read, it indicates the master is prepared toaccept data. Wait cycles are inserted until both IRDY# andTRDY# are asserted together.This pin is internally connected to a weak (>20-kohm) pull-upresistor.Target ReadyTRDY# is asserted to indicate that the target agent is able tocomplete the current data phase of the transaction. TRDY# isused in conjunction with IRDY#. A data phase is complete on anySYSCLK in which both TRDY# and IRDY# are sampledasserted. During a read, TRDY# indicates that valid data ispresent on AD[31:0]. During a write, it indicates the target is preparedto accept data. Wait cycles are inserted until both IRDY#andTRDY#areassertedtogether.This pin is internally connected to a weak (>20-kohm) pull-upresistor.Target StopSTOP# is asserted to indicate that the current target is requestingthe master to stop the current transaction. This signal is usedwith DEVSEL# to indicate retry, disconnect or target abort. IfSTOP# is sampled active while a master, FRAME# will be deassertedand the cycle will be stopped within three SYSCLKs.STOP# can be asserted in the following cases:• A PCI master tries to access memory that has been locked byanother master. This condition is detected if FRAME# andLOCK# are asserted during an address phase.• The PCI write buffers are full or a previously buffered cyclehas not completed.• Read cycles that cross cache line boundaries. This is conditionalbased upon the programming of bit 1 in the PCI ControlFunction 2 Register.This pin is internally connected to a weak (>20-kohm) pull-upresistor.Geode GXLV Processor SeriesRevision 1.3 33 www.national.com
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Power Management (Continued)CPU Sus
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Instruction Set (Continued)7.5 MMX
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Geode GXLV Processor Series Low Pow
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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