Geode GXLV Processor Series Low Power Integrated x86 Solutions

Geode GXLV Processor SeriesProcessor Programming (Continued)3.3.2.2 Configuration RegistersThe Configuration Registers listed in Table 3-9 are CPUregisters and are selected by register index numbers. Theregisters are accessed through I/O memory locations 22hand 23h. Registers are selected for access by writing anindex number to I/O Port 22h using an OUT instructionprior to transferring data through I/O Port 23h. This operationmust be atomic. The CLI instruction must be executedprior to accessing any of these registers.Index Type NameTable 3-9. Configuration Register SummaryEach data transfer through I/O Port 23h must be precededby a register index selection through I/O Port 22h; otherwise,subsequent I/O Port 23h operations are directed offchipand produce external I/O cycles.If MAPEN, bit 4 of CCR3 (Index C3h[4]) = 0, external I/Ocycles occur if the register index number is outside therange C0h-CFh, FEh, and FFh. The MAPEN bit shouldremain 0 during normal operation to allow system registerslocated at I/O Port 22h to be accessed (see Table 3-11 on page 52).AccessControlled By*DefaultValueReference(Bit Formats)C1h R/W CCR1 — Configuration Control 1 SMI_LOCK 00h Table 3-11 on page 52C2h R/W CCR2 — Configuration Control 2 -- 00h Table 3-11 on page 52C3h R/W CCR3 — Configuration Control 3 SMI_LOCK 00h Table 3-11 on page 52E8h R/W CCR4 — Configuration Control 4 MAPEN 85h Table 3-11 on page 53EBh R/W CCR7 — Configuration Control 7 -- 00h Table 3-11 on page 5320h R/W PCR — Performance Control MAPEN 07h Table 3-11 on page 53B0h R/W SMHR0 — SMM Header Address 0 MAPEN xxh Table 3-11 on page 54B1h R/W SMHR1 — SMM Header Address 1 MAPEN xxh Table 3-11 on page 54B2h R/W SMHR2 — SMM Header Address 2 MAPEN xxh Table 3-11 on page 54B3h R/W SMHR3 — SMM Header Address 3 MAPEN xxh Table 3-11 on page 54B8h R/W GCR — Graphics Control Register MAPEN 00h Table 4-1 on page 97B9h R/W VGACTL — VGA Control Register -- 00h Table 4-37 on page 163BAh-BDh R/W VGAM0 — VGA Mask Register -- 00h Table 4-37 on page 163CDh R/W SMAR0 — SMM Address 0 SMI_LOCK 00h Table 3-11 on page 54CEh R/W SMAR1 — SMM Address 1 SMI_LOCK 00h Table 3-11 on page 54CFh R/W SMAR2 — SMM Address 2 SMI_LOCK 00h Table 3-11 on page 54FEh RO DIR0 — Device ID 0 -- 4xh Table 3-11 on page 54FFh RO DIR1 — Device ID 1 -- xxh Table 3-11 on page 54Note: *MAPEN = Index C3h[4] (CCR3) and SMI_LOCK = Index C3h[0] (CCR3).www.national.com 50 Revision 1.3