Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesIntegrated Functions (Continued)The SDRAM interface timings are programmable. TheSHFTSDCLK bits in the MC_MEM_CNTRL2 register canbe used to change the relationship between SDCLK andthe control/address/data signals to meet setup and holdtime requirements for SDRAM across different board layouts.SHFTSDCLK bit values are selected based upon theSDRAM signals loads and the core frequency (refer toFigures 6-9 and 6-10 on page 202).Figure 4-10 shows an example of how the SHFTSDCLKbits setting affects SDCLK. The PCI clock is the inputclock to the GXLV processor. The core clock is the internalprocessor clock that is multiplied up. The memory controllerruns off this core clock. The memory clock is generatedby dividing down the core clock. SDCLK is generatedfrom the memory clock. In the example diagram, the processorclock is running 6X times the PCI clock and thememory clock is running in divide by 3 mode.The SDRAM control, address, and data signals are drivenoff edge “x 1 ” of the memory clock to be setup before edge“y 1 ”. With no shift applied, the control signals could end upbeing latched on edge “x 2 ” of the SDCLK. A shift value oftwo or three could be used so that SDCLK at the SDRAMis centered around when the control signals change.PCI ClockCore Clock(Internal)MemoryClock(Internal)0 1 2 3 4 5 6x 1 y 1CNTRLValidSDCLK(Note)x 2 y 2SDCLK(Note)Shift =4321 0Note: The first SDCLK shows how SDCLK operates with the SHFTSDCLK bits = 000, no shift.The second SDCLK shows how SDCLK operates with the SHFTSDCLK bits = 001, shift 0.5 core clock.(See MC_MEMCNTRL2 bits [5:3], Table 4-15 on page 114, for remaining decode values.)Figure 4-10. Effects of SHFTSDCLK Programming Bits Examplewww.national.com 124 Revision 1.3
Integrated Functions (Continued)4.4 GRAPHICS PIPELINEThe graphics pipeline of the GXLV processor contains a2D graphics accelerator. This hardware accelerator has aBitBLT/vector engine which dramatically improves graphicsperformance when rendering and moving graphicalobjects. Overall operating system performance isimproved as well. The accelerator hardware supports patterngeneration, source expansion, pattern/source transparency,and 256 ternary raster operations. The blockdiagram of the graphics pipeline is shown in Figure 4-11.4.4.1 BitBLT/Vector EngineBLTs are initiated by writing to the GP_BLT_MODE register,whichspecifiesthetypeofsourcedata(none,framebuffer, or BLT buffer), the type of the destination data(none, frame buffer, or BLT buffer), and a source expansionflag.Vectors are initiated by writing to theGP_VECTOR_MODE register (GX_BASE+8204h), whichspecifies the direction of the vector and a “read destinationdata” flag. If the flag is set, the hardware will readdestination data along the vector and store it temporarilyin the BLT Buffer 0.The BLT buffers use a portion of the L1 cache, called“scratchpad RAM”, to temporarily store source and destinationdata, typically on a scan line basis. See Section4.1.4.2 “Scratchpad RAM Utilization” for an explanation ofscratchpad RAM. The hardware automatically loadsframe-buffer data (source or destination) into the BLT buffersfor each scan line. The driver is responsible for makingsure that this does not overflow the memory allocated forthe BLT buffers. When the source data is a bitmap, thehardware loads the data directly into the BLT buffer at thebeginning of the BLT operation.Geode GXLV Processor SeriesScratchpad RAMandBitBLT BuffersC-BusOutput AlignerOutput AlignerGraphicsPipelinePatternHardwareSourceExpansionBE PAT BE SRC DSTControl LogicInternal BusInterface UnitRaster OperationDRAM InterfaceRegister AccessX-BusKey:BE = Byte EnablePAT = Pattern DataSRC = Source DataDST = Destination DataMemoryControllerFigure 4-11. Graphics Pipeline Block DiagramRevision 1.3 125 www.national.com
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Geode GXLV Processor Series Low Pow
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