Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesInstruction Set (Continued)Table 7-29. FPU Instruction Set Summary (Continued)FPU Instruction Opcode OperationClockCountFSUBRP Floating Point Subtract Reverse, Pop DE[11100n] ST(n)
Instruction Set (Continued)7.5 MMX INSTRUCTION SETThe CPU is functionally divided into the FPU unit, and theinteger unit. The FPU has been extended to process bothMMX instructions and floating point instructions in parallelwith the integer unit.For example, when the integer unit detects an MMXinstruction, the instruction passes to the FPU unit for execution.The integer unit continues to execute instructionswhile the FPU unit executes the MMX instruction. Ifanother MMX instruction is encountered, the secondMMX instruction is placed in the MMX queue. Up to fourMMX instructions can be queued.The MMX instruction set is summarized in Table 7-31. Theabbreviations used in the table are listed Table 7-30.Table 7-30. MMX Instruction Set Table LegendAbbreviationDescription
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Geode GXLV Processor SeriesArchitec
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Architecture Overview (Continued)Ge
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Architecture Overview (Continued)SD
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2.0 Signal DefinitionsThis section
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Signal Definitions (Continued)Index
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Signal Definitions (Continued)PinNo
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Signal Definitions (Continued)Table
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Signal Definitions (Continued)PinNo
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3.0 Processor ProgrammingThis secti
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Integrated Functions (Continued)4.1
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Integrated Functions (Continued)GX_
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Power Management (Continued)CPU Sus
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Power Management (Continued)5.2.2 I
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Geode GXLV Processor Series Low Power Integrated x86 Solutions

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