Geode GXLV Processor Series Low Power Integrated x86 Solutions

More documents

Recommendations

Info

Geode GXLV Processor SeriesPower Management (Continued)Table 5-2. Power Management Control and Status Registers (Continued)Bit Name DescriptionGX_BASE+8504h-8507h PM_CNTRL_TEN Register (R/W) Default Value = xxxxxx00h31:8 RSVD Reserved: These bits are not used. Do not write to these bits.7:6 RSVD Reserved: Set to 0.5 X_TEST (WO) Transmission Test (Write Only) : Setting this bit causes the GXLV processor to immediately transmitthe current contents of the serial packet. This bit is write only and is used primarily for test. Thisbit returns 0 on a read.4:3 X_FREQ Transmission Frequency: This field indicates the time between serial packet transmissions. Serialpacket transmissions occur at the selected interval only if at least one of the packet bits is set high:00 = Disable transmitter; 01 = 1 ms; 10 = 5 ms; 11 = 10 ms.2 CPU_RD CPU Activity Read Enable: Setting this bit high enables reporting of CPU level-1 cache readmisses that are not a result of an instruction fetch. This bit is a don’t-care if the CPU_EN bit is not sethigh.1 CPU_EN CPU Activity Master Enable: Setting this bit high enables reporting of CPU Level-1 cache missesin bit 6 of the serial transmission packet. When enabled, the CPU Level-1 cache miss activity isreported on any read (assuming the CPU_RD is set high) or write access excluding misses thatresulted from an instruction fetch.0 VID_EN Video Event Enable: Setting this bit high enables video decode events to be reported in bit 0 of theserial transmission packet. CPU or graphics-pipeline accesses to the graphics memory and displaycontroller-registeraccesses are also reported.GX_BASE+8508h-850Bh PM_CNTRL_CSTP Register (R/W) Default Value = xxxxxx00h31:8 RSVD Reserved: These bits are not used. Do not write to these bits.7:1 RSVD Reserved: Set to 0.0 CLK_STP Clock Stop: This bit configures the GXLV processor for Suspend Refresh Mode or 3 Volt SuspendMode:0 = Suspend Refresh Mode. The clocks to the memory and display controller remain active duringSuspend.1 = 3 Volt Suspend Mode. The external clock may be stopped during Suspend.Note: When bit 0 is set high and the Suspend input pin (SUSP#) is asserted, the GXLV processor stops all it’s internal clocks, andasserts the Suspend Acknowledge output pin (SUSPA#). Once SUSPA# is asserted the GXLV processor’s SYSCLK input canbe stopped. If bit 0 is cleared, the internal memory-controller and display-controller clocks are not stopped on theSUSP#/SUSPA# sequence, and the SYSCLK input can not be stopped.GX_BASE+850Ch-850Fh PM_SER_PACK Register (R/O) Default Value = xxxxxx00h31:8 RSVD Reserved: These bits are not used. Do not write to these bits.7 VID_IRQ Video IRQ: This bit indicates the occurrence of a video vertical sync pulse. This bit is set at thesame time that the VINT (Vertical Interrupt) bit is set in the DC_TIMING_CFG register. The VINT bithas a corresponding enable bit (VIEN) in the DC_TIM_CFG register (See Table 4-29 on page 145).6 CPU_ACT CPU Activity: This bit indicates the occurrence of a level 1 cache miss that was not a result of aninstruction fetch. This bit has a corresponding enable bit in the PM_CNTL_TEN register.5:2 RSVD Reserved: Set to 0.1 USR_DEF Programmable Address Decode: This bit indicates the occurrence of a programmable memoryaddress decode. This bit is set based on the values of the PM_BASE register and the PM_MASKregister (see Table 5-3 on page 183). The PM_BASE register can be initialized to any address in thefull 256 MB address range.0 VID_DEC Video Decode: This bit indicates that the CPU has accessed either the Display Controller registersor the graphics memory region. This bit has a corresponding enable bit in the PM_CNTRL_TEN.Note: The GXLV processor transmits the contents of the serial packet only when a bit in the packet register is set and the intervalcounter has elapsed. The Geode I/O companion decodes the serial packet after each transmission. Once a bit in the packet isset, it will remain set until the completion of the next packet transmission. Successive events of the same type that occurbetween packet transmissions are ignored. Multiple unique events between packet transmissions will accumulate in this register.www.national.com 182 Revision 1.3
Power Management (Continued)Table 5-3. Power Management Programmable Address Region RegistersBit Name DescriptionIndex FFFFFF6Ch PM_BASE Register (R/W) Default Value = 0000000h31:28 RSVD Reserved: Set to 0.27:2 BASE_ADDR Base Address: This is the word-aligned base address for the programmable memory range compare.The actual address range is determined with this field and the PM_MASK register value.1:0 RSVD Reserved: Set to 0.Index FFFFFF7Ch PM_MASK Register (R/W) Default Value = 0000000h31:28 RSVD Reserved: Set to 0.27:2 ADR_MASK Address Mask: This field is the address mask for the BASE_ADDR field in the PM_BASE register.If a bit in the ADR_MASK field is cleared the corresponding bit in the BASE_ADDR field must matchthe processor address. If a bit in the mask field is set high, the corresponding bit in the BASE_ADDRfield always compares. If the processor cycle type matches the values of the WE and RE bits, and allbits in the BASE_ADDR field match the processor address based on the ADR_MASK field, bit 1 willbe set high in the serial transmission packet.1 WE Write Enable: Compare memory write cycles with BASE_ADDR and ADR_MASK:0 = Disable; 1 = Enable.0 RE Read Enable: Compare memory read cycles with BASE_ADDR and ADR_MASK:0 = Disable; 1 = EnableGeode GXLV Processor SeriesRevision 1.3 183 www.national.com
Page 4 and 5:
Geode GXLV Processor SeriesTable of
Page 6 and 7:
Page 8:
Page 12 and 13:
Geode GXLV Processor SeriesArchitec
Page 15 and 16:
Architecture Overview (Continued)Ge
Page 17 and 18:
Architecture Overview (Continued)SD
Page 19 and 20:
2.0 Signal DefinitionsThis section
Page 21 and 22:
Signal Definitions (Continued)Index
Page 23 and 24:
Signal Definitions (Continued)PinNo
Page 25 and 26:
Signal Definitions (Continued)Table
Page 27 and 28:
Signal Definitions (Continued)PinNo
Page 29 and 30:
Signal Definitions (Continued)Table
Page 31 and 32:
Signal Definitions (Continued)2.2 S
Page 33 and 34:
Signal Definitions (Continued)2.2.2
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
3.0 Processor ProgrammingThis secti
Page 43 and 44:
Processor Programming (Continued)3.
Page 45 and 46:
Page 47 and 48:
Page 49 and 50:
Processor Programming (Continued)Bi
Page 51 and 52:
Processor Programming (Continued)Ta
Page 53 and 54:
Page 55 and 56:
Page 57 and 58:
Page 59 and 60:
Page 61 and 62:
Processor Programming (Continued)Th
Page 63 and 64:
Page 65 and 66:
Processor Programming (Continued)Ad
Page 67 and 68:
Page 69 and 70:
Processor Programming (Continued)Se
Page 71 and 72:
Page 73 and 74:
Processor Programming (Continued)TY
Page 75 and 76:
Processor Programming (Continued)Ta
Page 77 and 78:
Page 79 and 80:
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
Page 89 and 90:
Processor Programming (Continued)Wh
Page 91 and 92:
Page 93 and 94:
Page 95 and 96:
Page 97 and 98:
Integrated Functions (Continued)4.1
Page 99 and 100:
Page 101 and 102:
Integrated Functions (Continued)Mne
Page 103 and 104:
Page 105 and 106:
Integrated Functions (Continued)Bit
Page 107 and 108:
Page 109 and 110:
Page 111 and 112:
Integrated Functions (Continued)ACT
Page 113 and 114:
Page 115 and 116:
Page 117 and 118:
Page 119 and 120:
Integrated Functions (Continued)Tab
Page 121 and 122:
Integrated Functions (Continued)SDR
Page 123 and 124:
Page 125 and 126:
Page 127 and 128:
Page 129 and 130:
Page 131 and 132: Integrated Functions (Continued)Bit
Page 135 and 136: Integrated Functions (Continued)4.5
Page 137 and 138: Integrated Functions (Continued).Re
Page 139 and 140: Integrated Functions (Continued)640
Page 143 and 144: Integrated Functions (Continued)GX_
Page 145 and 146: Integrated Functions (Continued)11:
Page 147 and 148: Integrated Functions (Continued)Tab
Page 149 and 150: Integrated Functions (Continued)9:0
Page 163 and 164: Integrated Functions (Continued)Tab
Page 177 and 178: Power Management (Continued)CPU Sus
Page 179 and 180: Power Management (Continued)5.2.2 I
Page 181: Power Management (Continued)5.3 POW
Page 185 and 186: Electrical Specifications (Continue
Page 207 and 208: 7.0 Instruction SetThis section sum
Page 209 and 210: Instruction Set (Continued)7.1.2.3
Page 217 and 218: Instruction Set (Continued)Table 7-
Page 219 and 220: Instruction Set (Continued)Instruct
Page 221 and 222: Instruction Set (Continued)JMP Unco
Page 233 and 234:
Instruction Set (Continued)7.5 MMX
Page 235 and 236:
Instruction Set (Continued)PCMPEQB
Page 237 and 238:
Instruction Set (Continued)PUNPCKHW
Page 239 and 240:
Instruction Set (Continued)Table 7-
Page 241 and 242:
Package Specifications (Continued)C
Page 243 and 244:
Package Specifications (Continued)8
Page 245 and 246:
Package Specifications (Continued)S
Page 247:
Geode GXLV Processor Series Low Pow
show all

Geode GXLV Processor Series Low Power Integrated x86 Solutions

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?