Geode GXLV Processor Series Low Power Integrated x86 Solutions

Integrated Functions (Continued)4.1 INTEGRATED FUNCTIONS PROGRAMMING INTERFACEThe GXLV processor’s integrated functions programminginterface is a memory mapped space. The control registersfor the graphics pipeline, display controller, and memorycontroller are located in this space, as well as all thegraphics memory: frame buffer, compression buffer etc.This memory address space is referred to as the GXLVprocessor memory space.4.1.1 Graphics Control RegisterThe base address for these memory mapped registers isprogrammed in the Graphics Configuration Register(GCR, Index B8h, bits[1:0]), shown in Table 4-1. The GCRonly specifies address bits [31:30] of physical memory.The remaining address bits [29:0] are fixed to zero. TheGCR is I/O mapped because it must be accessed beforememory mapping can be enabled. Refer to Section3.3.2.2 “Configuration Registers” on page 50 for informationon how to access this register.The GXLV processor incorporates graphics functions thatrequire registers to implement and control them. Most ofthese registers are memory mapped and physicallylocated in the logical units they control. The mapping ofthese units is controlled by the GCR register.Figure 4-2 shows the complete memory address map forthe GXLV processor. When accessing the GXLV processormemory space, address bits [29:24] must be zero.This means that the GXLV processor accesses a linearaddress space with a total of 16 MB. Address bit 23divides this space into 8 MB for control (bit 23 = 0) and 8MB for graphics memory (bit 23 = 1). In control space, bits[22:16] are not decoded, so the programmer should setthem to zero. Address bit 15 divides the remaining 64 KBaddress space into scratchpad RAM and PCI access (bit15 = 0) and control registers (bit 15 = 1). Note thatscratchpad RAM is placed here by programming the tagsappropriately.Device drivers are responsible for performing physical-tovirtualmemory-address translation, including allocation ofselectors that point to the GXLV processor. All memorydecoded by the processor may be accessed in protectedmode by creating a selector with the physical addressequal to the GXLV Base Address which is shown in Table4-1, and a limit of 16 MB. Additionally, a selector with onlya 64 KB limit is large enough to access all of the GXLVprocessor’s registers and scratchpad RAM.Geode GXLV Processor SeriesTable 4-1. GCR RegisterBit Name DescriptionIndex B8h GCR Register (R/W) Default Value = 00h7:4 RSVD Reserved: Set to 0.3:2 SP Scratchpad Size: Specifies the size of the scratchpad cache.00 = 0 KB; Graphics instruction disabled (see Section 4.1.5 “Display Driver Instructions” on page 102).01 = 2 KB10 = 3 KB11 = 4 KB1:0 GX GXLV Base Address: Specifies the physical address for the base (GX_BASE) of the scratchpad RAM, thegraphics memory (frame buffer, compression buffer, etc.) and the other memory mapped registers.00 = Scratchpad RAM, graphics subsystem, and memory-mapped configuration registers are disabled.01 = Scratchpad RAM and control registers start at GX_BASE = 40000000h.10 = Scratchpad RAM and control registers start at GX_BASE = 80000000h.11 = Scratchpad RAM and control registers start at GX_BASE = C0000000h.Revision 1.3 97 www.national.com