Geode GXLV Processor Series Low Power Integrated x86 Solutions

More documents

Recommendations

Info

Geode GXLV Processor SeriesIntegrated Functions (Continued)convert the data in the VGA buffer to a separate 8-bppframe buffer that the hardware can use for display refresh.The remaining modes, VGA, EGA, and VESA, can be displayeddirectly by the hardware, with no data conversionrequired. For these modes, Virtual VGA often outperformstypical VGA cards because the frame buffer data does nottravel across an external bus.Display drivers for popular GUI (graphical user interface)based operating systems are provided by National Semiconductorwhich enable a full featured 2D hardware acceleratorto be used instead of the emulated VGA core.4.6.2.1 Datapath ElementsThe graphics controller contains several elements thatconvert between host data and frame buffer data.The rotator simply rotates the byte written from the hostby0to7bitstotheright,basedontheRotateCountfieldof the DataRotate register. It has no effect in the readpath.The display latch is a 32-bit register that is loaded onevery read access to the frame buffer. All 32 bits of theframe buffer DWORDs are loaded into the latch.The write-mode unit converts a byte from the host into a32-bit value. A VGA has four write modes:• Write Mode 0:- Bitnofbytebcomesfromoneoftwoplaces,depending on bit b of the EnableSetReset register. Ifthat bit is zero, it comes from bit n of the host data. Ifthat bit is one, it comes from bit b of the SetResetregister. This mode allows the programmer to setsome planes from the host data and the others fromSetReset.• Write Mode 1:- All 32 bits come directly out of the display latch; thehost data is ignored. This mode is used for screento-screencopies.• Write Mode 2:- Bit n of byte b comes from bit b of the host data; thatis, the four LSBs of the host data are each replicatedthrough a byte of the result. In conjunction with theBitMask register, this mode allows the programmerto directly write a 4-bit color to one or more pixels.• Write Mode 3:- Bit n of byte b comes from bit b of the SetResetregister. The host data is ANDed with the BitMaskregister to provide the bit mask for the write (seebelow).The read mode unit converts a 32-bit value from theframe buffer into a byte. A VGA has two read modes:• Read Mode 0:- One of the four bytes from the frame buffer isreturned, based on the value of the ReadMapSelectregister. In Chain 4 mode, bits [1:0] of the readaddress select a plane. In odd/even read mode, bit 0of the read address replaces bit 0 of ReadMapSelect.• Read Mode 1:- Bit n of the result is set to 1 if bit n in every byte bmatches bit b of the ColorCompare register; otherwiseit is set to 0. There is a ColorDon’tCare registerthat can exclude planes from this comparison. Infour-plane graphics modes, this provides a conversionfrom 4 bpp to 1 bpp.The ALU is a simple two-operand ROP unit that operateson writes. Its operating modes are COPY, AND, OR, andXOR. The 32-bit inputs are:1) the output of the write-mode unit and2) the display latch (not necessarily the value at theframe buffer address of the write).An application that wishes to perform ROPs on the sourceand destination must first byte read the address (to loadthe latch) and then immediately write a byte to the sameaddress. The ALU has no effect in Write Mode 1.The bit mask unit does not provide a true bit mask.Instead, it selects between the ALU output and the displaylatch. The mask is an 8-bit value, and bit n of the maskmakes the selection for bit n of all four bytes of the result(a zero selects the latch). No bit masking occurs in WriteMode 1.The VGA hardware of the GXLV processor does notimplement Write Mode 1 directly, but it can be indirectlyimplemented by setting the BitMask to zero and the ALUmode to COPY. This is done by the SMM code so thereare no compatibility issues with applications.4.6.2.2 GXLV VGA HardwareThe GXLV processor core contains hardware to detectVGA accesses and generate SMI interrupts. The graphicspipeline contains hardware to detect and process readsand writes to VGA memory. The VGA memory on theGXLV processor is partitioned from system memory. TheGXLV processor has the following hardware componentsto assist the VGA emulation software.• SMI Generation• VGA Range Detection• VGA Sequencer• VGA Write/Read Path• VGA Address Generator• VGA Memorywww.national.com 160 Revision 1.3
Integrated Functions (Continued)4.6.2.3 SMI GenerationVGA emulation software is notified of VGA memoryaccesses by an SMI generated in dedicated circuitry inthe processor core that detects and traps memoryaccesses. The SMI generation hardware for VGA memoryaddresses is in the second stage of instruction decodingon the processor core. This is the earliest stage of instructiondecode where virtual addresses have been translatedto physical addresses. Trapping after the execution stageis impractical, because memory write buffering will allowsubsequent instructions to execute.The VGA emulation code requires the SMI to be generatedimmediately when a VGA access occurs. The SMIgeneration hardware can optionally exclude areas of VGAmemory, based on a 32-bit register which has a control bitfor each 2 KB region of the VGA memory window. Thecontrol bit determines whether or not an SMI interrupt isgenerated for the corresponding region. The purpose ofthis hardware is to allow the VGA emulation software todisable SMI interrupts in VGA memory regions that arenot currently displayed.For direct display modes (8 bpp or 16 bpp) in the displaycontroller, Virtual VGA can operate without SMI generation.The SMI generation circuit on the GXLV processor hasconfiguration registers to control and mask SMI interruptsin the VGA memory space.4.6.2.4 VGA Range DetectionThe VGA range detection circuit is similar to the SMI generationhardware, however, it resides in the internal businterface address mapping unit. The purpose of this hardwareis to notify the graphics pipeline when accesses tothe VGA memory range A0000h to BFFFFh are detected.The graphics pipeline has VGA read and write path hardwareto process VGA memory accesses. The VGA rangedetection can be configured to trap VGA memoryaccesses in one or more of the following ranges: A0000hto AFFFFh (EGA,VGA), B0000h to B7FFFh (MDA), orB8000h to BFFFFh (CGA).4.6.2.5 VGA SequencerThe VGA sequencer is located at the front end of thegraphics pipeline. The purpose of the VGA sequencer isto divide up multiple-byte read and write operations into asequence of single-byte read and write operations. 16-bitor 32-bit X-bus write operations to VGA memory aredivided into 8-bit write operations and sent to the VGAwrite path. 16-bit or 32-bit X-bus read operations fromVGA memory are accumulated from 8-bit read operationsover the VGA read path. The sequencer generates thelower two bits of the address.4.6.2.6 VGA Write/Read PathThe VGA write path implements standard VGA write operationsinto VGA memory. No SMI is generated for writepath operations when the VGA access is not displayed.When the VGA access is displayed, an SMI is generatedso that the SMI emulation can update the frame buffer.The VGA write path converts 8-bit write operations fromthe sequencer into 32-bit VGA memory write operations.The operations performed by the VGA write path includedata rotation, raster operation (ALU), bit masking, planeselect, plane enable, and write modes.The VGA read path implements standard VGA read operationsfrom VGA memory. No SMI is needed for read-pathoperations. The VGA read path converts 32-bit read operationsfrom VGA memory to 8-bit data back to thesequencer. The basic operations performed by the VGAread path include color compare, plane-read select, andread modes.4.6.2.7 VGA Address GeneratorThe VGA address generator translates VGA memoryaddresses up to the address where the VGA memoryresides on the GXLV processor. The VGA address generatorrequires the address from the VGA access (A0000hto BFFFFh), the base of the VGA memory on the GXLVprocessor, and various control bits. The control bits arenecessary because addressing is complicated byodd/even and Chain 4 addressing modes.4.6.2.8 VGA MemoryThe VGA memory requires 256 KB of memory organizedas 64 KB by 32 bits. The VGA memory is implemented aspart of system memory. The GXLV processor partitionssystem memory into two areas, normal system memoryand graphics memory. System memory is mapped to thenormal physical address of the DRAM, starting at zeroand ending at memory size. Graphics memory is mappedinto high physical memory, contiguous to the registers anddedicated cache of the GXLV processor. The graphicsmemory includes the frame buffer, compression buffer,cursor memory, and VGA memory. The VGA memory ismapped on a 256 KB boundary to simplify the addressgenerationGeode GXLV Processor SeriesRevision 1.3 161 www.national.com
Page 4 and 5:
Geode GXLV Processor SeriesTable of
Page 6 and 7:
Page 8:
Page 12 and 13:
Geode GXLV Processor SeriesArchitec
Page 15 and 16:
Architecture Overview (Continued)Ge
Page 17 and 18:
Architecture Overview (Continued)SD
Page 19 and 20:
2.0 Signal DefinitionsThis section
Page 21 and 22:
Signal Definitions (Continued)Index
Page 23 and 24:
Signal Definitions (Continued)PinNo
Page 25 and 26:
Signal Definitions (Continued)Table
Page 27 and 28:
Signal Definitions (Continued)PinNo
Page 29 and 30:
Signal Definitions (Continued)Table
Page 31 and 32:
Signal Definitions (Continued)2.2 S
Page 33 and 34:
Signal Definitions (Continued)2.2.2
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
3.0 Processor ProgrammingThis secti
Page 43 and 44:
Processor Programming (Continued)3.
Page 45 and 46:
Page 47 and 48:
Page 49 and 50:
Processor Programming (Continued)Bi
Page 51 and 52:
Processor Programming (Continued)Ta
Page 53 and 54:
Page 55 and 56:
Page 57 and 58:
Page 59 and 60:
Page 61 and 62:
Processor Programming (Continued)Th
Page 63 and 64:
Page 65 and 66:
Processor Programming (Continued)Ad
Page 67 and 68:
Page 69 and 70:
Processor Programming (Continued)Se
Page 71 and 72:
Page 73 and 74:
Processor Programming (Continued)TY
Page 75 and 76:
Processor Programming (Continued)Ta
Page 77 and 78:
Page 79 and 80:
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
Page 89 and 90:
Processor Programming (Continued)Wh
Page 91 and 92:
Page 93 and 94:
Page 95 and 96:
Page 97 and 98:
Integrated Functions (Continued)4.1
Page 99 and 100:
Page 101 and 102:
Integrated Functions (Continued)Mne
Page 103 and 104:
Page 105 and 106:
Integrated Functions (Continued)Bit
Page 107 and 108:
Page 109 and 110: Integrated Functions (Continued)4.3
Page 111 and 112: Integrated Functions (Continued)ACT
Page 113 and 114: Integrated Functions (Continued)Bit
Page 119 and 120: Integrated Functions (Continued)Tab
Page 121 and 122: Integrated Functions (Continued)SDR
Page 137 and 138: Integrated Functions (Continued).Re
Page 139 and 140: Integrated Functions (Continued)640
Page 143 and 144: Integrated Functions (Continued)GX_
Page 145 and 146: Integrated Functions (Continued)11:
Page 149 and 150: Integrated Functions (Continued)9:0
Page 159: Integrated Functions (Continued)4.6
Page 177 and 178: Power Management (Continued)CPU Sus
Page 179 and 180: Power Management (Continued)5.2.2 I
Page 181 and 182: Power Management (Continued)5.3 POW
Page 183 and 184: Power Management (Continued)Table 5
Page 185 and 186: Electrical Specifications (Continue
Page 207 and 208: 7.0 Instruction SetThis section sum
Page 209 and 210: Instruction Set (Continued)7.1.2.3
Page 211 and 212:
Instruction Set (Continued)7.1.5.2
Page 213 and 214:
Page 215 and 216:
Page 217 and 218:
Instruction Set (Continued)Table 7-
Page 219 and 220:
Instruction Set (Continued)Instruct
Page 221 and 222:
Instruction Set (Continued)JMP Unco
Page 223 and 224:
Page 225 and 226:
Page 227 and 228:
Page 229 and 230:
Page 231 and 232:
Page 233 and 234:
Instruction Set (Continued)7.5 MMX
Page 235 and 236:
Instruction Set (Continued)PCMPEQB
Page 237 and 238:
Instruction Set (Continued)PUNPCKHW
Page 239 and 240:
Page 241 and 242:
Package Specifications (Continued)C
Page 243 and 244:
Package Specifications (Continued)8
Page 245 and 246:
Package Specifications (Continued)S
Page 247:
Geode GXLV Processor Series Low Pow
show all

Geode GXLV Processor Series Low Power Integrated x86 Solutions

Create successful ePaper yourself

Delete template?

Save as template?