Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesIntegrated Functions (Continued)4.5.10 Timing RegistersThe Display Controller’s timing registers control the generationof sync, blanking, and active display regions. Theyprovide complete flexibility in interfacing to both CRT andflat panel displays. These registers will generally be programmedby the BIOS from an INT 10h call or by theextended mode driver from a display timing file. Note thatthe horizontal timing parameters are specified in characterclocks, which actually means pixels divided by 8, since allBit Name DescriptionTable 4-31. Display Controller Timing Registerscharacters are bit mapped. For interlaced display the verticalcounter will be incremented twice during each displayline, so vertical timing parameters should be programmedwith reference to the total frame rather than a single field.The Timing Registers group consists of six 32-bit registerslocated at GX_BASE+8330h-834Ch. These registers aresummarized in Table 4-28 on page 141, and Table 4-31gives their bit formats.GX_BASE+8330h-8333h DC_H_TIMING_1 Register (R/W) (Locked) Default Value = xxxxxxxxh31:27 RSVD Reserved: Set to 0.26:19 H_TOTAL Horizontal Total: The total number of character clocks for a given scan line minus 1. Note that thevalue is necessarily greater than the H_ACTIVE field because it includes border pixels and blankedpixels. For flat panels, this value will never change. The field [26:16] may be programmed with thepixel count minus 1, although bits [18:16] are ignored. The horizontal total is programmable on 8-pixel boundaries only.18:16 IGRD Ignored15:11 RSVD Reserved: Set to 0.10:3 H_ACTIVE Horizontal Active: The total number of character clocks for the displayed portion of a scan lineminus 1. The field [10:0] may be programmed with the pixel count minus 1, although bits [2:0] areignored. The active count is programmable on 8-pixel boundaries only. Note that for flat panels, ifthis value is less than the panel active horizontal resolution (H_PANEL), the parametersH_BLANK_START, H_BLANK_END, H_SYNC_START, and H_SYNC_END should be reduced bythe value of H_ADJUST (or the value of H_PANEL - H_ACTIVE / 2)to achieve horizontal centering.2:0 IGRD IgnoredNote: For simultaneous CRT and flat panel display the H_ACTIVE and H_TOTAL parameters pertain to both.GX_BASE+8334h-8337h DC_H_TIMING_2 Register (R/W) (Locked) Default Value = xxxxxxxxh31:27 RSVD Reserved: Set to 0.26:19 H_BLK_END Horizontal Blank End: The character clock count at which the horizontal blanking signal becomesinactive minus 1. The field [26:16] may be programmed with the pixel count minus 1, although bits[18:16] are ignored. The blank end position is programmable on 8-pixel boundaries only.18:16 IGRD Ignored15:11 RSVD Reserved: Set to 0.10:3 H_BLK_START Horizontal Blank Start: The character clock count at which the horizontal blanking signal becomesactive minus 1. The field [10:0] may be programmed with the pixel count minus 1, although bits [2:0]are ignored. The blank start position is programmable on 8-pixel boundaries only.2:0 IGRD IgnoredNote: A minimum of four character clocks are required for the horizontal blanking portion of a line in order for the timing generator tofunction correctly.GX_BASE+8338h-833Bh DC_H_TIMING_3 Register (R/W) (Locked) Default Value = xxxxxxxxh31:27 RSVD Reserved: Set to 0.26:19 H_SYNC_END Horizontal Sync End: The character clock count at which the CRT horizontal sync signal becomesinactive minus 1. The field [26:16] may be programmed with the pixel count minus 1, although bits[18:16] are ignored. The sync end position is programmable on 8-pixel boundaries only.18:16 IGRD Ignored15:11 RSVD Reserved: Set to 0.10:3 H_SYNC_START Horizontal Sync Start: The character clock count at which the CRT horizontal sync signal becomesactive minus 1. The field [10:0] may be programmed with the pixel count minus 1, although bits [2:0]are ignored. The sync start position is programmable on 8-pixel boundaries only.2:0 IGRD IgnoredNote: This register should also be programmed appropriately for flat panel only display since the horizontal sync transition determineswhen to advance the vertical counter.www.national.com 150 Revision 1.3
Integrated Functions (Continued)Bit Name DescriptionGX_BASE+833Ch-833Fh C_FP_H_TIMING Register (R/W) (Locked) Default Value = xxxxxxxxh31:27 RSVD Reserved: Set to 0.26:16 FP_H_SYNC_END15:11 RSVD Reserved: Set to 0.10:0 FP_H_SYNC_STARTTable 4-31. Display Controller Timing Registers (Continued)Flat Panel Horizontal Sync End: The pixel count at which the flat panel horizontal sync signalbecomes inactive minus 1.Flat Panel Horizontal Sync Start: The pixel count at which the flat panel horizontal sync signalbecomes active minus 1.Note: These values are specified in pixels rather than character clocks to allow precise control over sync position. For flat panelswhich combine two pixels per panel clock, these values should be odd numbers (even pixel boundary) to guarantee that thesync signal will meet proper setup and hold times.Geode GXLV Processor SeriesGX_BASE+8340h-8343h DC_V_TIMING_1 Register (R/W) (Locked) Default Value = xxxxxxxxh31:27 RSVD Reserved: Set to 0.26:16 V_TOTAL Vertical Total: The total number of lines for a given frame scan minus 1. The value is necessarilygreater than the V_ACTIVE field because it includes border lines and blanked lines. If the display isinterlaced, the total number of lines must be odd, so this value should be an even number.15:11 RSVD Reserved: Set to 0.10:0 V_ACTIVE Vertical Active: The total number of lines for the displayed portion of a frame scan minus 1. For flatpanels, if this value is less than the panel active vertical resolution (V_PANEL), the parametersV_BLANK_START, V_BLANK_END, V_SYNC_START, and V_SYNC_END should be reduced bythe following value (V_ADJUST) to achieve vertical centering: V_ADJUST = (V_PANEL –V_ACTIVE) / 2If the display is interlaced, the number of active lines should be even, so this value should be an oddnumber.Note: These values are specified in lines.GX_BASE+8344h-8347h DC_V_TIMING_2 Register (R/W) (Locked) Default Value = xxxxxxxxh31:27 RSVD Reserved: Set to 0.26:16 V_BLANK_END Vertical Blank End: The line at which the vertical blanking signal becomes inactive minus 1. If thedisplay is interlaced, no border is supported, so this value should be identical to V_TOTAL.15:11 RSVD Reserved: Set to 0.10:0 V_BLANK_STARTVertical Blank Start: The line at which the vertical blanking signal becomes active minus 1. If thedisplay is interlaced, this value should be programmed to V_ACTIVE plus 1.Note: These values are specified in lines. For interlaced display, no border is supported, so blank timing is implied by the total/activetiming.GX_BASE+8348h-834Bh DC_V_TIMING_3 Register (R/W) (Locked) Default Value = xxxxxxxxh31:27 RSVD Reserved: Set to 0.26:16 V_SYNC_END Vertical Sync End: The line at which the CRT vertical sync signal becomes inactive minus 1.15:11 RSVD Reserved: Set to 0.10:0 V_SYNC_START Vertical Sync Start: The line at which the CRT vertical sync signal becomes active minus 1. Forinterlaced display, note that the vertical counter is incremented twice during each line and sincethere are an odd number of lines, the vertical sync pulse will trigger in the middle of a line for onefield and at the end of a line for the subsequent field.Note: These values are specified in lines.GX_BASE+834Ch-834Fh DC_FP_V_TIMING Register (R/W) (Locked) Default Value = xxxxxxxxh31:27 RSVD Reserved: Set to 0.26:16 FP_V_SYNC_END15:11 RSVD Reserved: Set to 0.10:0 FP_VSYNC_STARTNote: These values are specified in lines.Flat Panel Vertical Sync End: The line at which the flat panel vertical sync signal becomes inactiveminus 2. Note that the internal flat panel vertical sync is latched by the flat panel horizontal syncprior to being output to the panel.Flat Panel Vertical Sync Start: The line at which the internal flat panel vertical sync signalbecomes active minus 2. Note that the internal flat panel vertical sync is latched by the flat panelhorizontal sync prior to being output to the panel.Revision 1.3 151 www.national.com
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Geode GXLV Processor Series Low Pow
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