Geode GXLV Processor Series Low Power Integrated x86 Solutions

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Geode GXLV Processor SeriesInstruction Set (Continued)7.2 CPUID INSTRUCTIONThe CPUID instruction (opcode 0FA2) allows the softwareto make processor inquiries as to the vendor, family,model, stepping, features and also provides cache information.The GXLV supports both the standard andNational Semiconductor extended CPUID levels.The presence of the CPUID instruction is indicated by theability to change the value of the ID Flag, bit 21 in theEFLAGS register.The CPUID level allows the CPUID instruction to returndifferent information in the EAX, EBX, ECX, and EDX registers.The level is determined by the initialized value ofthe EAX register before the instruction is executed. Asummary of the CPUID levels is shown in Table 7-16.CPUIDTypeTable 7-16. CPUID Levels SummaryInitializedEAXRegisterReturned Data in EAX, EBX,ECX, EDX RegistersStandard 0000 0000h Maximum standard levels, CPUvendor stringStandard 0000 0001h Model, family, type and featuresStandard 0000 0002h TLB and cache informationExtended 8000 0000h Maximum extended levelsExtended 8000 0001h Extended model, family, type andfeaturesExtended 8000 0002h CPU marketing name stringExtended 8000 0003hExtended 8000 0004hExtended 8000 0005h TLB and L1 cache description7.2.1.1 CPUID Instruction with EAX = 0000 0000hStandard function 0h (EAX = 0) of the CPUID instructionreturns the maximum standard CPUID levels as well asthe processor vendor string.After the instruction is executed, the EAX register containsthe maximum standard CPUID levels supported. Themaximum standard CPUID level is the highest acceptablevalue for the EAX register input. This does not include theextended CPUID levels.The EBX through EDX registers contain the vendor stringof the processor as shown in Table 7-17.Table 7-17. CPUID Data Returned when EAX = 0Register(Note) Returned Contents DescriptionEAX 2 Maximum StandardLevelEBX 69 72 7943 Vendor ID String 1(iryC)EDX 73 6E 4978 Vendor ID String 2(snlx)ECX 64 61 6574 Vendor ID String 3(daet)Note: The register column is intentionally out of order.7.2.1 Standard CPUID LevelsThe standard CPUID levels are part of the standard x86instruction set.www.national.com 212 Revision 1.3
Instruction Set (Continued)7.2.1.2 CPUID Instruction with EAX = 00000001hStandard function 01h (EAX = 1) of the CPUID instructionreturns the processor type, family, model, and steppinginformation of the current processor in the EAX register(see Table 7-18). The EBX and ECX registers arereserved.Table 7-18. EAX, EBX, ECX CPUID DataReturned when EAX = 1RegisterReturnedContentsDescriptionEAX[3:0] xx Stepping IDEAX[7:4] 4 ModelEAX[11:8] 5 FamilyEAX[15:12] 0 TypeEAX[31:16] - ReservedEBX - ReservedECX - ReservedThe standard feature flags supported are returned in theEDX register as shown in Table 7-19. Each flag refers to aspecific feature and indicates if that feature is present onthe processor. Some of these features have protectioncontrol in CR4. Before using any of these features on theprocessor, the software should check the correspondingfeature flag. Attempting to execute an unavailable featurecan cause exceptions and unexpected behavior. Forexample, software must check EDX bit 4 before attemptingto use the Time Stamp Counter instruction.Table 7-19.EDX CPUID Data Returned whenEAX = 1EDXReturnedContents* Feature FlagCR4BitEDX[0] 1 FPU On-Chip -EDX[1] 0 Virtual Mode Extension -EDX[2] 0 Debug Extensions -EDX[3] 0 Page Size Extensions -EDX[4] 1 Time Stamp Counter 2EDX[5] 1 RDMSR / WRMSR-InstructionsEDX[6] 0 Physical Address-ExtensionsEDX[7] 0 Machine Check Exception -EDX[8] 1 CMPXCHG8B Instruction -EDX[9] 0 On-Chip APIC Hardware -EDX[10] 0 Reserved -EDX[11] 0 SYSENTER / SYSEXIT -InstructionsEDX[12] 0 Memory Type Range -RegistersEDX[13] 0 Page Global Enable -Table 7-19.EDXEDX CPUID Data Returned whenEAX = 1 (Continued)ReturnedContents*Feature FlagEDX[14] 0 Machine Check-ArchitectureEDX[15] 1 Conditional Move-InstructionsEDX[16] 0 Page Attribute Table -EDX[22:17] 0 Reserved -EDX[23] 1 MMX Instructions -EDX[24] 0 Fast FPU Save and-RestoreEDX[31:25] 0 Reserved -Note: *0 = Not Supported7.2.1.3 CPUID Instruction with EAX = 00000002hStandard function 02h (EAX = 02h) of the CPUID instructionreturns information that is specific to the NationalSemiconductor family of processors. Information aboutthe TLB is returned in EAX as shown in Table 7-20. Informationabout the L1 cache is returned in EDX.Table 7-20. Standard CPUID withEAX = 00000002hCR4BitRegisterReturnedContents DescriptionEAX xxxx70xxh TLBis32entry,4-waysetassociative,and has 4 KB pages.EAX xx xx xx 01h The CPUID instruction needs tobe executed only once with aninput value of 02h to retrievecomplete information about thecache and TLB.EBXReservedECXReservedEDX xx xx xx 80h L1 cache is 16 KB, 4-way setassociated, and has 16 bytes perline.Geode GXLV Processor SeriesRevision 1.3 213 www.national.com
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