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18-10 Industrial Communication Systems<br />

NTP<br />

θ C<br />

θ R<br />

Phase<br />

detector<br />

V d<br />

Clock filter<br />

VS<br />

VFO<br />

Loop filter<br />

x<br />

V c<br />

Clock adjust<br />

y<br />

Predictor<br />

FIGURE 18.7 NTP clock discipline (NTPClockDiscipline.pdf). (Redrawn from Mills, D., IEEE/ACM Trans.<br />

Netw., 6(5), 505, 1998.)<br />

x<br />

Phase<br />

correct<br />

y PLL<br />

PLL predict<br />

V S<br />

y<br />

Frequency<br />

y adj<br />

Σ<br />

y FLL<br />

FLL predict<br />

FIGURE 18.8 NTP phase and frequency prediction functions (NTPPredictionFunctions.pdf). (Redrawn from<br />

Mills, D., IEEE/ACM Trans. Netw., 6(5), 505, 1998.)<br />

prediction (Figure 18.8). The phase-locked loop (PLL) predicts a frequency offset as integral of V S τ, whereas<br />

the frequency-locked loop (FLL) use an exponential average of V S /τ. These two values are combined via a<br />

simple summarization. It has to be specifically noted that the averaging interval of these two components is<br />

chosen with respect to the Allan-intercept, in order to gain an optimal behavior of the structure.<br />

References<br />

[Anceaume1997] Anceaume, E. and Puaut, I.A., Taxonomy of clock synchronization algorithms, Campus<br />

Universitaire de Beaulieu, Rennes Cedex, France, 1997, 25 pp.<br />

[Brennan2005] Brennan, R.W., Christensen, J.H., Gruver, W.A., Kotak, D.B., Norrie, D.H., and van<br />

Leeuwen, E.H., Holonic manufacturing <strong>systems</strong>: A technical overview, in The Industrial Information<br />

Technology Handbook, Part II (Industrial Information Technology), Section 7 (Integration<br />

Technologies), Chapter 106, CRC Press, Boca Raton, FL, 2005, 106-1–106-15.<br />

[Eidson2005] Eidson, J. C., The application of IEEE 1588 to test & measurement <strong>systems</strong>, White Paper<br />

Agilent, Agilent Laboratories, Palo Alto, CA, December 2005, pp. 9–13.<br />

[Eidson2006] Eidson, J.C., Measurement, Control, and Communication Using IEEE 1588, Springer,<br />

London, U.K., 2006.<br />

[Gaderer2004] Gaderer, G. and Sauter, T., Strategies for clock synchronization in powerline networks, in<br />

Proceedings of the 3rd International Workshop on Real-Time Networks in Conjunction with the 16th<br />

Euromicro International Conference on Real-Time Systems, Catania, Italy, 2004.<br />

© <strong>2011</strong> by Taylor and Francis Group, LLC

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