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24-10 Industrial Communication Systems<br />

e1<br />

e2<br />

e3<br />

e4<br />

v6, v8<br />

v7, v9<br />

vx, v1<br />

v2, v3<br />

S1<br />

S3<br />

v6, v8, v9<br />

v6, v7<br />

vx, v2<br />

e5<br />

v5<br />

v1, v3<br />

e6<br />

v4<br />

S2<br />

S4<br />

S5<br />

v6, v8, v9<br />

vx, v6, v7<br />

v2, v5<br />

v1, v3, v4<br />

e7<br />

e8<br />

e9<br />

e10<br />

FIGURE 24.8<br />

Example of AFDX VLs configuration.<br />

The AFDX network architecture is composed of several interconnected switches. The inputs and outputs<br />

of the network are the end <strong>systems</strong> (the little circles in Figure 24.7). Each end system is connected to<br />

exactly one switch port and each switch port is connected to either an end system or another switch. The<br />

links are all full duplex. In Figure 24.7, the values on the end <strong>systems</strong> indicate the number of VL that are<br />

dispatched between the end <strong>systems</strong> and a given switch. Thus, the VL concept of virtual <strong>communication</strong><br />

channels has the advantage of statically defining the flows, which enter the network, and associating<br />

some performance properties to each flow. Each VL can be statically mapped on the network of interconnected<br />

AFDX switches. Transmitting an Ethernet frame from one end system to another is based<br />

on a VL identifier, which is used for the deterministic routing of each VL (the switch forwarding tables<br />

are statically defined after allocation of all VL on the AFDX network architecture). Each VL defines a<br />

logical unidirectional connection from one source end system to one or more destination end <strong>systems</strong>.<br />

For example, Figure 24.8 illustrates different kinds of VL: vx is a unicast VL with path {e3−S3−S4−e8},<br />

while v6 is a multicast VL with paths {e1−S1−S2−e7} and {e1−S1−S4−e8}.<br />

A VL definition includes the bandwidth allocation gap (BAG) value, the minimum frame size (S min ),<br />

and the maximum frame size (S max ). The BAG is the minimum delay between two consecutive frames<br />

of the associated VL (which actually defines a VL as a sporadic flow). BAG and S max values guarantee an<br />

allocated bandwidth for each VL. Moreover, a jitter value is associated to each VL to establish an upper<br />

bound on the maximum admissible jitter after multiplexing different regulated VL flows.<br />

24.6.4 Virtual Link Properties<br />

From the avionics <strong>systems</strong> designer’s point of view, classic ARINC 429 buses have many interesting<br />

features. For example, the single-emitter assumption implies a dedicated link offered to the emitter, and<br />

thus guaranteed access to the bus, guaranteed bandwidth, and high determinism. Moreover, the <strong>communication</strong><br />

paradigm used by many avionic applications is derived from the ARINC 429’s properties<br />

behavior, which has been generalized on IMA through APEX port paradigm [ARI97]. This explains why<br />

the VL concept is of importance in the definition of AFDX; it allows direct replacement of ARINC 429<br />

buses, on a deterministic ARINC 664 network.<br />

24.6.4.1 VL Bandwidth Guarantee<br />

Each avionic function defines its VL bandwidth requirements in the form of two parameters: the BAG<br />

and the maximum frame size (S max ). When the VL has no jitter, the BAG represents the minimum<br />

interval between the first bits of two consecutive frames. Thus, the bandwidth offered to a VL is the one<br />

obtained when emitting a maximum-sized frame every BAG, the latter being specified by an integer (k), to<br />

give (create) a 2 k interval (in milliseconds). The minimal BAG is thus 1.ms for k = 0, and when combined<br />

with standard maximum Ethernet frames, the maximum bandwidth offered attributed to a single VL<br />

can be up to 12.Mbps.<br />

The network integrator collates all the VL bandwidth requirements and verifies that the sum of VL<br />

bandwidths on any physical link of the full-duplex switched Ethernet network does not exceed the<br />

© <strong>2011</strong> by Taylor and Francis Group, LLC

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