wilamowski-b-m-irwin-j-d-industrial-communication-systems-2011

Ethernet POWERLINK 39-9
typically in the order of some microseconds. The EPL protocol may also have a total hardware support,
typically via FPGA technology. In this case, the EPL packet handler, the Ethernet controller, and the hub
(if included) are completely embedded in hardware. The processing of incoming requests, in this case, is
entirely carried out in hardware, and the interconnection between the Ethernet controller and the EPL
packet handler can use dedicated buses, leading to extremely shorter response times, below 1.μs.
Similarly to the jitter, the use of tree or linear topologies with several cascaded hubs also has a negative
impact on the TAT since each hub situated between the MN and a CN adds its own delay. Moreover, it has
to be noticed that the hub-induced delay affects both the MN requests and the CN replies, doubling in such
a way its impact in each query of the CN.
In general, the TAT in a transaction involving node i can be upper bounded as
TAT i = DCN i + × Dhub × Nhub i + tprop + CReq + CRes
2 (39.2)
where
D i CN is the nominal response time of the ith CN
D hub is the nominal hub delay (homogeneous hubs assumed for simplification)
N i hub is the number of hubs involved in a transaction between the MN and the ith CN
t prop is the wire-propagation time
C Req is the transmission time of the request message
C Res is the transmission time of the corresponding response message
As an example, a transaction in which the MN polls a CN having a short amount of data to transmit
(up to 36 data bytes) may be considered. In this case, C Req = C Res = 6.72.μs. Assuming also a fast CN
(i.e., with hardware support) yielding a 1.μs response time, a single hub with 400.ns delay, and that the
segment (wire) length is of 100.m (leading to t prop = 500.ns), the TAT, given by Equation 39.2, is (in seconds):
TAT = 1× 10 + 2 × ( 400 × 10 + 500 × 10 ) + 2 × 6. 72 × 10 = 16. 24 × 10
−6 −9 −9 −6 −6
If a two-hub topology is considered, the above computed value of TAT is increased by 800.ns, corresponding
to a relative degradation of about 4.9% on the TAT. For a linear topology with 10 devices, the total increase
would be around 22.2%. These performance figures show how the network topology design may have a
substantial impact on the TAT.
The use of switch devices may significantly worsen the performance. Indeed, cut-through switches
induce a latency of at least 12.μs since message forwarding only starts after the reception of the destination
address Ethernet field, thus multiplying the latency for a factor of at least 3. For store-and-forward
switches, the latency time depends on the message size and can be very relevant (up to 120.μs per switch,
if maximum size Ethernet messages are employed).
39.7.3 Cycle Time
The cycle time is a factor of paramount importance since EPL applications (for example, those concerned
with motion control issues) may require very short cycle times (well below 1.ms, as discussed in [14]). The cycle
time of EPL may be trivially calculated as the sum of the periods shown in Figure 39.2:
TC = Tst + Tis + Tac + Tid
(39.3)
where the addends in Equation 39.3 represent the durations of the start, isochronous, asynchronous, and
idle periods, respectively. However, the EPL cycle time is mostly determined by the duration of the isochronous
period which, in its turn, is a direct function of the number of queries to the configured CNs.
© 2011 by Taylor and Francis Group, LLC